ST72F63BE1M1 STMicroelectronics, ST72F63BE1M1 Datasheet - Page 104

• Manufacturer Part Number: ST72F63BE1M1
• Description: IC MCU 8BIT 4K FLASH 24-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F63BE1M1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-SOIC (7.5mm Width)
• Data Converters: A/D 12x8b
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MDTU3-EPB/US, ST7MDTULS-EVAL, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
• Minimum Operating Temperature: 0 C
• For Use With: 497-5521 - EVAL BOARD LOW SPEED USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

On-chip peripherals
Note:
104/186
Endpoint n register A (EPnRA)
These registers (EP0RA, EP1RA and EP2RA) are used for controlling data transmission.
They are also reset by the USB bus reset.
Endpoint 2 and the EP2RA register are not available on some devices (see device feature
list and register map).
Reset value: 0000 xxxx (0xh)
Table 34.
OUT
ST_
7
STAT_TX1
0
0
1
1
[5:4] STAT_TX[1:0] Status bits, for transmission transfers.
[3:0] TBC[3:0] Transmit byte count for Endpoint n.
STAT_TX bit definition
7 ST_OUT Status out.
6 DTOG_TX Data Toggle, for transmission transfers.
DTOG
_TX
This bit is set by software to indicate that a status out packet is expected: in this
case, all nonzero OUT data transfers on the endpoint are STALLed instead of being
ACKed. When ST_OUT is reset, OUT transactions can have any number of bytes,
as needed.
It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next
transmitted data packet. This bit is set by hardware at the reception of a SETUP
PID. DTOG_TX toggles only when the transmitter has received the ACK signal from
the USB host. DTOG_TX and also DTOG_RX (see EPnRB) are normally updated
by hardware, at the receipt of a relevant PID. They can be also written by software.
These bits contain the information about the endpoint status, which are listed in
Table
These bits are written by software. Hardware sets the STAT_TX bits to NAK when a
correct transfer has occurred (CTR=1) related to a IN or SETUP transaction
addressed to this endpoint; this allows the software to prepare the next set of data
to be transmitted.
Before transmission, after filling the transmit buffer, software must write in the TBC
field the transmit packet size expressed in bytes (in the range 0-8).
Caution: Any value outside the range 0-8 willinduce undesired effects (such as
34.
STAT_TX0
continuous data transmission).
STAT
_TX1
0
1
0
1
Doc ID 7516 Rev 8
_TX0
STAT
DISABLED: transmission transfers cannot be
executed.
STALL: the endpoint is stalled and all transmission
requests result in a STALL handshake.
NAK: the endpoint is naked and all transmission
requests result in a NAK handshake.
VALID: this endpoint is enabled for transmission.
Read.write
TBC3
Meaning
TBC2
TBC1
ST7263Bxx
TBC0
0