ST72F63BE1M1 STMicroelectronics, ST72F63BE1M1 Datasheet - Page 38
ST72F63BE1M1
Manufacturer Part Number
ST72F63BE1M1
Description
IC MCU 8BIT 4K FLASH 24-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BE1M1
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
24-SOIC (7.5mm Width)
Data Converters
A/D 12x8b
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
14
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST7MDTULS-EVAL, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
For Use With
497-5521 - EVAL BOARD LOW SPEED USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Interrupts
Note:
38/186
1
2
3
Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
●
●
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by one of the two following operations:
●
●
The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be
enabled) will therefore be lost if the clear sequence is executed.
All interrupts allow the processor to leave the Wait low power mode.
Exit from Halt mode may only be triggered by an external interrupt on one of the ITi ports
(PA4-PA7 and PB4-PB7), an end suspend mode interrupt coming from USB peripheral, or a
reset.
Figure 19. Interrupt processing flowchart
FROM RESET
The I bit of the CC register is cleared.
The corresponding enable bit is set in the control register.
Writing “0” to the corresponding bit in the status register.
Accessing the status register while the flag is set followed by a read or write of an
associated register.
EXECUTE INSTRUCTION
Doc ID 7516 Rev 8
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
FETCH NEXT INSTRUCTION
N
BIT I SET
IRET
Y
Y
N
LOAD PC FROM INTERRUPT VECTOR
N
STACK PC, X, A, CC
INTERRUPT
SET I BIT
Y
ST7263Bxx
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