Z8PE003SZ010EG Zilog, Z8PE003SZ010EG Datasheet - Page 22

• Manufacturer Part Number: Z8PE003SZ010EG
• Description: IC MICROCONTROLLER 1K 18-SOIC
• Manufacturer: Zilog
• Series: Z8® Plusr

Specifications of Z8PE003SZ010EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4294; Z8PE003SZ010EG

Z8PE003
Z8Plus OTP Microcontroller
Note: The
The
low:
WDT Time Select (D6, D5, D4).
the time-out period. Table 13 indicates the range of time-
out values that can be obtained. The default values of
D5
time-out period when coming out of
WDT During HALT (D7).
not the
tive during
ting the part while halted. Coming out of
is enabled during
POWER-DOWN MODES
In addition to the standard RUN mode, the Z8Plus MCU
supports two Power-Down modes to minimize device cur-
HALT MODE OPERATION
The
off the internal CPU clock. The on-chip oscillator circuit
remains active so the internal clock continues to run and is
applied to the timers and interrupt logic.
To enter
struction. It is not necessary to execute a
immediately before the
22
, and
TCTLHI
HALT
7F
struction out of the
within the device detects that it is in the process of exe-
cuting the first instruction after the processor leaves
SET
five bits of the
first instruction, hardware does not allow the upper five
bits of this register to be written.
WDT
D4
HALT
. During the execution of this instruction, the upper
WDT
mode suspends instruction execution and turns
HALT
are
bits for control of the
is active during
HALT
mode, the device only requires a
001
can only be disabled via software if the first in-
mode. A
HALT
, which sets the
TCTLHI
HALT
mode.
RESET
This bit determines whether or
0
register can be written. After this
; enter HALT mode
prevents the
HALT
instruction.
performs this function. Logic
Bits 6, 5, and 4 determine
mode. A
WDT
WDT
RESET
RESET
are described be-
WDT
NOP
to its minimum
1
.
indicates ac-
from reset-
instruction
, the
HALT
P R E L I M I N A R Y
WDT
D6
RE-
in-
,
STOP MODE (D3).
STOP
STOP
RESET
NOP
mode.
Bits 2, 1 and 0.
rent consumption. The two modes supported are
STOP
HALT
nal interrupt. The first instruction executed is the interrupt
service routine. At completion of the interrupt service rou-
tine, the user program continues from the instruction after
the
The
or a Watch-Dog Timer (
gram execution restarts at
D6
0
0
0
0
1
1
1
1
Note:
HALT
HALT
. If bit D3 is cleared, the
.
mode can be exited by servicing an external or inter-
mode, bit D3 must be cleared immediately at leaving
D5
0
0
1
1
0
0
1
1
mode is disabled. If an application requires use of
*TpC is an XTAL clock cycle. The default at reset is 001.
. If bit D3 is set, the
instruction.
mode can also be exited via a
D4
0
1
0
1
0
1
0
1
Table 13. WDT Time-Out
These bits are reserved and must be
Crystal Clocks*
to Timeout
Disabled
65,536 TpC
131,072 TpC
262,144 TpC
524,288 TpC
1,048,576 TpC
2,097,152 TpC
8,388,608 TpC
Coming out of
WDT
0020H
STOP
STOP
) time-out. In these cases, pro-
, the reset restart address.
instruction executes as a
instruction enters
DS007500-Z8X0399
RESET
Time-Out Using
a 10-MHz Crystal
Disabled
6.55 ms
13.11 ms
26.21 ms
52.43 ms
104.86 ms
209.72 ms
838.86 ms
RESET
, the device
HALT
activation
ZiLOG
STOP
0
.
and