ST72C254G2M6 STMicroelectronics, ST72C254G2M6 Datasheet - Page 121
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ST72C254G2M6
Manufacturer Part Number
ST72C254G2M6
Description
IC MCU 8BIT 8K FLASH SOIC-28
Manufacturer
STMicroelectronics
Series
ST7r
Datasheets
1.INDART-ST72C254.pdf
(3 pages)
2.ST72C104G1M6.pdf
(141 pages)
3.ST72C215G2M6.pdf
(140 pages)
Specifications of ST72C254G2M6
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3.2 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
ST7
No. Of I/o's
22
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
ST72C2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
3 bit
Operating Supply Voltage
3.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDT1-DVP2/US
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72C254G2M6
Manufacturer:
ST
Quantity:
20 000
14.9 CONTROL PIN CHARACTERISTICS
14.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V
Figure 86. Typical Application with RESET pin
Notes:
1. Unless otherwise specified, typical data are based on T
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The I
(I/O ports and control pins) must not exceed I
5. The R
scribed in
6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on
RESET pin with a duration below t
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environments.
8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
t
w(RSTL)out
t
t
Symbol
h(RSTL)in
g(RSTL)in
V
R
V
V
V
EXTERNAL
CIRCUIT
hys
ON
OL
IH
IL
RESET
USER
IO
ON
current sunk must always respect the absolute maximum rating specified in
Figure
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Output low level voltage
(see
Weak pull-up equivalent resistor
Generated reset pulse duration
External reset pulse hold time
Filtered glitch duration
pull-up equivalent resistor is based on a resistive transistor (corresponding I
8)
Figure
87). This data is based on characterization results, not tested in production.
V
DD
0.1 F
0.1 F
88,
Parameter
V
Figure
DD
4.7k
h(RSTL)in
2)
89)
7)
2)
4)
6)
can be ignored.
5)
VSS
3)
.
DD
V
V
External pin or
internal reset sources
, f
DD
IN
RESET
OSC
=5V
8)
V
A
ST72104G, ST72215G, ST72216G, ST72254G
Conditions
SS
=25°C and V
, and T
R
ON
I
I
V
V
IO
IO
DD
DD
V
=+5mA
=+2mA
DD
=5V
=3.4V
A
unless otherwise specified.
DD
=5V.
0.7xV
Min
20
80
20
DD
Section 14.2.2
ON
Typ
0.68
0.28
400
100
40
30
6
current characteristics de-
1)
INTERNAL
RESET CONTROL
WATCHDOG RESET
LVD RESET
0.3xV
and the sum of I
Max
0.95
0.45
120
100
60
DD
ST72XXX
1/f
121/140
Unit
SFOSC
mV
k
ns
V
V
s
s
IO