ST72C254G2M6 STMicroelectronics, ST72C254G2M6 Datasheet - Page 82

• Manufacturer Part Number: ST72C254G2M6
• Description: IC MCU 8BIT 8K FLASH SOIC-28
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72C254G2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3.2 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: ST7
• No. Of I/o's: 22
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: ST72C2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3 bit
• Operating Supply Voltage: 3.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MDT1-DVP2/US
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition

ST72104G, ST72215G, ST72216G, ST72254G
I
Bit 1 = M/SL Master/Slave.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
Bit 0 = SB Start bit (Master mode).
This bit is set by hardware as soon as the Start
condition
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DR register. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No Start condition
1: Start condition generated
I
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 = AF Acknowledge failure .
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
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2
2
C BUS INTERFACE (Cont’d)
C STATUS REGISTER 2 (SR2)
7
0
0
is
0
generated
AF
STOPF ARLO BERR GCAL
(following
a
write
0
Bit 2 = ARLO Arbitration lost .
This bit is set by hardware when the interface los-
es the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by soft-
ware reading SR2 register or by hardware when
the interface is disabled (PE=0).
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Bit 1 = BERR Bus error.
This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. An inter-
rupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the in-
terface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Bit 0 = GCAL General Call (Slave mode).
This bit is set by hardware when a general call ad-
dress is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
(STOPF=1) or when the interface is disabled
(PE=0).
0: No general call address detected on bus
1: general call address detected on bus