Z86C9620VSC Zilog, Z86C9620VSC Datasheet
Z86C9620VSC
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Z86C9620VSC Summary of contents
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... Clock Speeds: 16 and 20 MHz On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, or External Clock Drive The Z86C61/62/96 architecture is characterized by Zilog’s 8-bit microcontroller core. The device offers a flexible I/O scheme, an efficient register and address space structure, multiplexed capabilities between address/data, I/O, and a number of ancillary features that are useful in many indus- trial and advanced scientific applications ...
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... Register File 256 x 8-Bit Port Address or I/O (Nibble Programmable) Figure 1. Z86C61 Functional Block Diagram PS003501-0301 Circuit Device GND V SS /AS /DS R//W /RESET Machine Timing and Instruction Control Prg. Memory 16,384 x 8-Bit Program Counter Port 1 8 Address/Data or I/O (Byte Programmable) DS97Z8X1600 Zilog ...
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... Zilog Port 6 Port 5 I/O (Bit Programmable) DS97Z8X1600 Output Input Port 3 UART Counter/ Timers (2) Interrupt Control Port 2 Port 4 I/O (Bit Programmable) (Nibble Programmable) Figure 2. Z86C62 Functional Block Diagram PS003501-0301 Z86C61/62/96 CMOS Z8 Microcontroller Vcc GND XTAL /AS /DS R//W /RESET Machine Timing and Instruction Control ...
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... Figure 3. Z86C96 Functional Block Diagram PS003501-0301 Vcc GND XTAL /AS /DS R//W /RESET Machine Timing and Instruction Control ALU Flags Register Pointer Program Counter Register File 256 x 8-Bit Port 0 Port Address or I/O Address/Data or I/O (Byte Programmable) Z-BUS When Used As Address/Data Bus DS97Z8X1600 Zilog ...
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... Zilog PIN DESCRIPTION 1 VCC XTAL2 XTAL1 P37 P30 /RESET R//W /DS /AS P35 DIP 40 - Pin GND P32 P00 P01 P02 P03 P04 P05 P06 20 P07 Figure 4. Z86C61 40-Pin DIP Pin Assignments DS97Z8X1600 Table 1. Z86C61 40-Pin DIP Pin Identification Pin # Symbol 21 P36 ...
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... Input 39 N/C Input 40-42 P25-P27 Output 43 P31 Output 44 P36 Output Output Input Input In/Output Input In/Output PS003501-0301 Zilog NC P24 P23 P22 P21 P20 P33 P34 P17 P16 P15 Function Direction Port 1, Pins 0,1,2,3,4 In/Output Not Connected Input Port 1, Pins 5,6,7 In/Output ...
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... Zilog 1 P44 VCC P45 XTAL2 XTAL1 P37 P30 NC /RESET R//W /DS P46 P47 /AS P35 R//RL GND P32 P50 P51 P00 P01 P02 P03 P04 P05 P06 P07 VCC P52 P53 P54 32 Figure 6. Z86C62/C96 64-Pin DIP Pin Assignments DS97Z8X1600 Table 3. Z86C62/C96 64-Pin DIP Pin Identification ...
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... P47 /P1DS /AS /DTimers P35 R//RL GND P32 P50 P51 P00 P01 P02 Figure 7. Z86C62/C96 68-Pin PLCC Pin Assignments PLCC 68 - Pin PS003501-0301 Zilog 61 60 P24 P23 P22 P60 P61 P21 P20 SCLK /SYNC GND P33 P34 P62 P63 P17 P16 44 P15 43 DS97Z8X1600 ...
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... Zilog Table 4. Z86C62/C96 68-Pin PLCC Pin Identification Pin # Symbol 1-2 P44-P43 P45 5 XTAL2 6 XTAL1 7 P37 8 P30 9 /RESET 10 R//W 11 /P0DS 12 /DS 13-14 P47-P46 15 /P1DS 16 /AS 17 /DTIMER 18 P35 19 R//RL 20 GND 21 P32 22-23 P51-P50 24-31 P07-P00 33-36 P55-P52 37-38 P11-P10 39-40 ...
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... This is a stress rating only; operation of the device at +150 C any condition above those indicated in the operational sec- tions of these specifications is not implied. Exposure to ab- † solute maximum rating conditions for an extended period may affect device reliability. Figure 8. Test Load Diagram PS003501-0301 Zilog I DS97Z8X1600 ...
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... Zilog DC ELECTRICAL CHARACTERISTICS Z86C61/62/96 Sym Parameter Max Input Voltage V Clock Input High 0. Voltage V Clock Input Low Voltage V Input High Voltage IH V Input Low Voltage Output High Voltage OH V Output High Voltage OH V Output Low Voltage OL V Output Low Voltage OL V Reset Input High ...
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... Z86C61/62/96 CMOS Z8 Microcontroller DC ELECTRICAL CHARACTERISTICS (Continued) R//W Port 0, /DM Port 1 /AS /DS (Read) Port /DS (Write OUT Figure 9. External I/O or Memory Read/Write PS003501-0301 Zilog DS97Z8X1600 ...
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... Zilog AC CHARACTERISTICS External I/O or Memory Read and Write Timing Z86C61/62/96 (16 MHz) No Symbol 1 TdA(AS) Address Valid to /AS rise Delay 2 TdAS(A) /AS rise to Address Float Delay 3 TdAS(DR) /AS rise to Read Data Req’d Valid 4 TwAS /AS Low Width 5 TdAZ(DS) Address Float to /DS fall 6 TwDSR /DS (Read) Low Width ...
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... T = -40°C to +105° MHz Min Max Min 120 105 150 PS003501-0301 Zilog 20 MHz Max Units Notes ns 2,3 ns 2,3 120 ns 1,2,3 ns 2,3 ns 105 ns 1,2,3 ns 1,2,3 ns 1,2,3 ns 2,3 ns 2,3 ns 2,3 ns 2,3 ns 2,3 ns 2,3 ns 2,3 150 ns 1,2,3 ns 2,3 ns 2,3 DS97Z8X1600 ...
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... Zilog AC CHARACTERISTICS Additional Timing Diagram Clock 7 TIN IRQN DS97Z8X1600 Figure 10. Additional Timing PS003501-0301 Z86C61/62/96 CMOS Z8 Microcontroller ...
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... TA = -40°C to +105°C A 20/16 MHz Min Max 50/62.5 1000 50/62 TpC 5 TpC 8 TpC 8 TpC 100 70 5 TpC 5 TpC 5 TpC 5 TpC for a logic 1 and 0.8V for a logic PS003501-0301 20/16 MHz Min Max Units Notes 1000 100 2,4 ns 2,5 ns 2,3 DS97Z8X1600 Zilog ...
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... Zilog AC CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid 1 /DAV (Input) RDY (Output) Data Out 7 /DAV (Output) RDY (Input) DS97Z8X1600 Next Data In Valid 2 3 Delayed DAV 4 Figure 11. Input Handshake Timing Data Out Valid Figure 12. Output Handshake Timing PS003501-0301 Z86C61/62/96 CMOS Z8 Microcontroller 5 6 Delayed RDY ...
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... TdRDY0d(DAV) RDY rise to DAV fall Delay 0°C to +70°C A 20/16 MHz Parameter Min Max 0 145 110 115 115 0 TpC 0 115 110 115 PS003501-0301 Zilog T = –40° +105°C 20/16 MHZ Data Min Max Direction 0 IN 145 IN 110 IN 115 IN 115 TpC OUT ...
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... Zilog PIN FUNCTIONS R//RL (input, active Low). This pin when connected to GND disables the internal ROM and forces the device to function as a Z86C96 ROMless Z8. (Note: When left un- connected or pulled High to VCC the part functions as a normal Z86C61/62 ROM version.) This pin is only avail- able on the 44-pin version of the Z86C61, and both ver- sions of the Z86C62 ...
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... Z86C61/62/96 CMOS Z8 Microcontroller PIN FUNCTIONS (Continued) MCU OEN Out TTL Level Shifter Port 0 (I/O) 4 Handshake Controls /DAV0 and RDY0 (P32 and P35) R 500 K Figure 13. Port 0 Configuration PS003501-0301 Zilog PAD Auto Latch DS97Z8X1600 ...
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... Zilog Port 1 (P17-P10). Port 8-bit, byte programmable, bidirectional, TTL compatible port. It has multiplexed Ad- dress (A7-A0) and Data (D7-D0) ports. For Z86C61/62/96, these eight I/O lines can be programmed as Input or Out- put lines or can be configured under software control as an address/data port for interfacing external memory. When used as an I/O port, Port 1 may be placed under hand- shake control ...
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... RDY2. The handshake sig- nal assignment for Port 3 lines P31 and P36 is dictated by the direction (input or output) assigned to P27 (Figure 15). Port 2 (I/O) Handshake Controls /DAV2 and RDY2 (P31 and P36) R 500 K Figure 15. Port 2 Configuration PS003501-0301 Zilog PAD Auto Latch DS97Z8X1600 ...
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... Zilog Port 3 (P37-P30). Port 8-bit, CMOS-compatible four-fixed input and four-fixed output port. These eight I/O lines have four-fixed (P33-P30) input and four-fixed (P37- MCU Out In DS97Z8X1600 P34) output ports. Port 3, when used as serial I/O, are pro- grammed as serial in and serial out, respectively (Figure 16) ...
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... If parity is on, bit 7 of the received data is replaced by a parity error flag. Received characters gen- erate the IRQ3 interrupt request. Note: UART function is only available in standard timing mode (i.e., P01M PS003501-0301 Zilog UART Ext Serial In D/R ...
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... Zilog Transmitted Data (No Parity Transmitted Data (With Parity DS97Z8X1600 Received Data (No Parity Start Bit Eight Data Bits Two Stop Bits Received Data (With Parity Start Bit Seven Data Bits Odd Parity Two Stop Bits Figure 17. Serial Data Formats PS003501-0301 Z86C61/62/96 CMOS Z8 Microcontroller ...
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... Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs that are not externally driven. This reduces excessive supply current flow in the input buffer when it is not being driven by any source. Port 4 (I/O) R 500 K Figure 18. Port 4 Configuration PS003501-0301 Zilog PAD Auto Latch DS97Z8X1600 ...
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... Zilog FUNCTIONAL DESCRIPTION Address Space Program Memory. The Z86C61/62 can address external program memory (Figure 19). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that cor- respond to the six available interrupts. For ROM mode, byte 13 to byte 16383 consists of on-chip ROM ...
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... Expanded Register Group R244 Working Register Group R243 R242 R241 R240 R239 PS003501-0301 Zilog Identifiers SPL Stack Pointer (Bits 7-0) SPH Stack Pointer (Bits 15-8) RP Register Pointer FLAGS Program Control Flags IMR Interrupt Mask Register IRQ Interrupt Request Register IPR Interrupt Priority Register ...
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... Zilog Figure 23. Expanded Register File Architecture DS97Z8X1600 PS003501-0301 Z86C61/62/96 CMOS Z8 Microcontroller 1 29 ...
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... The ROM Protect option is mask-programmable se- lected by the customer at the time when the ROM code is submitted PS003501-0301 Zilog Set working group 0 and Bank F Load value into Port 4 using working register addressing. Load value into Port 4 using absolute addressing. Load value into Port 6 mode. ...
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... Zilog The upper nibble of the register file address provided by the register pointer specifies the active working-register group. FF Register Group F F0 • • • • • • • • • • • • • Specified Working • Register Group Register Group 1 10 ...
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... Initial Value Register Write Write Internal Data Bus Figure 25. Counter/Timer Block Diagram PS003501-0301 Read T0 T0 Current Value Register Register 8-bit Down Counter IRQ4 Serial I/O Clock ÷2 Tout P36 8-Bit IRQ5 Down Counter T1 T1 Current Value Register Register Read DS97Z8X1600 Zilog ...
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... Zilog Interrupts. The Z86C61/62/96 has six different interrupts from eight different sources. The interrupts are maskable and prioritized. The eight sources are divided as follows: four sources are claimed by Port 3 lines P33-P30, one in Serial Out, one is Serial In, and two in the counter/timers (Figure 26). The Interrupt Mask Register globally or indi- vidually enables or disables the six interrupt requests ...
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... To do this, the user must execute a NOP (opcode=0FFH) immediately before the appropri- ate sleep instruction, i.e PS003501-0301 XTAL1 XTAL2 External Clock NOP ; clear the pipeline STOP ; enter STOP mode or NOP ; clear the pipeline HALT ; enter HALT mode DS97Z8X1600 Zilog ...
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... Zilog Z8 CONTROL REGISTER DIAGRAMS R240 SIO Figure 28. Serial I/O Register (F0H: Read/Write) R241 TMR Figure 29. Timer Mode Register (F1H: Read/Write) R242 Initial Value T1 Current Value Figure 30. Counter/Timer1 Register (F2H: Read/Write) DS97Z8X1600 R243 PRE1 Serial Data (D0 = LSB Function 1 Load T0 0 Disable T0 Count ...
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... R249 IPR P34 = RDY1//DAV1 P31 = Input (TIN) P36 = Output (TOUT) 1 P31 = /DAV2/RDY2 P36 = RDY2//DAV2 0 P30 = Input P37 = Output 1 P30 = Serial In P37 = Serial Out 0 Parity Off 1 Parity On Figure 37. Interrupt Priority Register PS003501-0301 Zilog Mode Output 01 Input Stack Selection 0 External 1 Internal ...
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... Zilog R250 IRQ IRQ0 = P32 Input (D0 = IRQ0) IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = P30 Input, Serial Input IRQ4 = T0 IRQ5 = T1 Reserved (Must be 0) Figure 38. Interrupt Request Register (FAH: Read/Write) R251 IMR Figure 39. Interrupt Mask Register (FBH: Read/Write) R252 FLAGS Figure 40. Flag Register ...
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... Reserved (Must be 0) (F) 06: (Write Only) Data 0 Defines Level 0 1 Defines Level 1 Reserved (Must be 0) (F) 07: (Read/Write P60 - P63 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input* Reserved (Must be 0) (F) 08: (Write Only) 0 Port 6 Open-drain* 1 Port 6 Push-pull (F) 09: (Write Only) DS97Z8X1600 Zilog ...
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... Zilog PACKAGE INFORMATION DS97Z8X1600 Figure 52. 40-Pin DIP Package Diagram Figure 53. 44-Pin PLCC Package Diagram PS003501-0301 Z86C61/62/96 CMOS Z8 Microcontroller 1 39 ...
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... Z86C61/62/96 CMOS Z8 Microcontroller PACKAGE INFORMATION (Continued) 40 Figure 54. 64-Pin DIP Package Diagram PS003501-0301 Zilog DS97Z8X1600 ...
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... Zilog DS97Z8X1600 Figure 55. 68-Pin PLCC Package Diagram PS003501-0301 Z86C61/62/96 CMOS Z8 Microcontroller 1 41 ...
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... Z86C6216PSC Z86C6216VSC 20 MHz 64-pin DIP 68-pin PLCC Z86C9620PSC Z86C9620VSC For fast results, contact your Zilog sales office for assis- tance in ordering the part desired. Example: Z 86C61 © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc ...