Z86C9620VSC Zilog, Z86C9620VSC Datasheet - Page 33

• Manufacturer Part Number: Z86C9620VSC
• Description: IC Z8 20MHZ C91 W/7 PORTS 68PLCC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86C9620VSC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, UART/USART
• Number Of I /o: 52
• Program Memory Type: ROMless
• Ram Size: 236 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Peripherals: -

Zilog
Interrupts. The Z86C61/62/96 has six different interrupts
from eight different sources. The interrupts are maskable
and prioritized. The eight sources are divided as follows:
four sources are claimed by Port 3 lines P33-P30, one in
Serial Out, one is Serial In, and two in the counter/timers
(Figure 26). The Interrupt Mask Register globally or indi-
vidually enables or disables the six interrupt requests.
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All Z86C61/62/96
interrupts are vectored through locations in the program
memory. When an interrupt machine cycle is activated, an
interrupt request is granted. Thus, this disables all of the
subsequent interrupts, saves the Program Counter and
Status Flags, and then branches to the program memory
vector location reserved for that interrupt. This memory lo-
cation and the next byte contain the 16-bit address of the
interrupt service routine for that particular interrupt re-
quest.
DS97Z8X1600
Interrupt
Request
Figure 26. Interrupt Block Diagram
PS003501-0301
Interrupt
Enable
Global
P R E L I M I N A R Y
To accommodate polled interrupt systems, interrupt inputs
are masked and the Interrupt Request register is polled to
determine which of the interrupt requests need service.
Software initialed interrupts are supported by setting the
appropriate bit in the Interrupt Request Register (IRQ).
Internal interrupt requests are sampled on the falling edge
of the last cycle of every instruction. The interrupt request
must be valid 5TpC before the falling edge of the last clock
cycle of the currently executing instruction.
For the ROMless mode, when the device samples a valid
interrupt request, the next 48 (external) clock cycles are
used to prioritize the interrupt, and push the two PC bytes
and the FLAG register onto the stack. The following nine
cycles are used to fetch the interrupt vector from external
memory. The first byte of the interrupt service routine is
fetched beginning on the 58th TpC cycle following the in-
ternal sample point, which corresponds to the 63rd TpC
cycle following the external interrupt sample point.
Vector Select
IRQ0 - IRQ5
PRIORITY
LOGIC
IMR
IRQ
IPR
CMOS Z8 Microcontroller
6
Z86C61/62/96
33
1