ST10R272LT6 STMicroelectronics, ST10R272LT6 Datasheet - Page 30

• Manufacturer Part Number: ST10R272LT6
• Description: IC MCU 16BIT LV ROMLESS 100-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R272LT6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10R2x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-2045

ST10R272L - SERIAL CHANNELS
11
Serial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with different functionality, an Asynchronous/
Synchronous Serial Channel (ASC0) and a Synchronous Serial Port (SSP).
ASC0
A dedicated baud rate generator sets up standard baud rates without oscillator tuning. 3
separate interrupt vectors are provided for transmission, reception, and erroneous reception.
In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start
bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism
to distinguish address from data bytes has been included (8-bit data + wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift
clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back
option is available for testing purposes.
A number of optional hardware error detection capabilities have been included to increase the
reliability of data transfers. A parity bit can be generated automatically on transmission, or
checked on reception. Framing error detection recognizes data frames with missing stop bits.
An overrun error is generated if the last character received was not read out of the receive
buffer register at the time the reception of a new character is complete.The table below lists
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1
CPU Clock
CPU Clock
CAPIN
T5EUD
T6EUD
SERIAL CHANNELS
T5IN
T6IN
2
2
n
n
n=2...9
n=2...9
T6
Mode
T5
Mode
Figure 9 GPT2 block diagram
Capture
Clear
GPT2 Tim er T6
GPT2 Tim er T5
GPT2 CAPREL
U/D
U/D
Reload
Toggle FF
T60TL
Interrupt
Request
Interrupt
Request
Interrupt
Request
T6OUT