STM32F102RBT6 STMicroelectronics, STM32F102RBT6 Datasheet - Page 50

• Manufacturer Part Number: STM32F102RBT6
• Description: MCU ARM 32BIT 128KB FLASH 64LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F102RBT6

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 51
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: 497-10030 - STARTER KIT FOR STM32497-8853 - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL - KIT IAR KICKSTART STM32 CORTEXM3497-8512 - KIT STARTER FOR STM32F10XE MCU497-8505 - KIT STARTER FOR STM32F10XE MCU497-8304 - KIT STM32 MOTOR DRIVER BLDC497-6438 - BOARD EVALUTION FOR STM32 512K497-6289 - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U - BOARD EVAL MCBSTM32 + ULINK2497-6053 - KIT STARTER FOR STM32497-6052 - KIT STARTER FOR STM32497-6050 - KIT STARTER FOR STM32497-6049 - KIT EVALUATION LOW COST STM32497-6048 - BOARD EVALUATION FOR STM32497-6047 - KIT DEVELOPMENT FOR STM32497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-8312

Electrical characteristics
5.3.13
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Figure 20. I/O AC characteristics definition
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in
performed under ambient temperature and V
Table
Table 36.
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
Figure 21. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
V
V
V
V
V
NF(NRST)
IH(NRST)
Symbol
IL(NRST)
F(NRST)
to the series resistance must be minimum
Table
hys(NRST)
R
8.
PU
36. Otherwise the reset will not be taken into account by the device.
(1)
(1)
(1)
PU
(1)
External
reset circuit
NRST pin characteristics
(see
EXT ERNAL
OUTPUT
ON 50pF
NRST Input low level voltage
NRST Input high level voltage
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse
Maximum frequency is achieved if (t r + t f ) 2/3)T and if the duty cycle is (45-55%)
Table
(1)
0.1 µF
33).
Parameter
t r(I O)out
NRST
Doc ID 15056 Rev 3
(2)
(~10% order)
10%
V DD
50%
when loaded by 50pF
R PU
90%
(2)
.
DD
Conditions
supply voltage conditions summarized in
V
T
IN
10%
Table 36

V
50%
SS
Filter
90%
t r(I O)out
STM32F102x8, STM32F102xB
STM32F10xxx
–0.5
are derived from tests
IL(NRST)
Min
300
30
Internal Reset
2
max level specified in
Typ
200
40
V
DD
ai14132c
Max
100
0.8
50
+0.5
ai14131
Unit
mV
k
ns
ns
V