ST10F276Z5Q3 STMicroelectronics, ST10F276Z5Q3 Datasheet - Page 220

• Manufacturer Part Number: ST10F276Z5Q3
• Description: MCU 16BIT 832KB FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5Q3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Interface Type: CAN/I2C
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24-ch x 10-bit
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-5580

Electrical characteristics
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CLKOUT and READY
V
Table 108. CLKOUT and READY
1. These timings are given for characterization purposes only, in order to assure recognition at a specific
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCLs must be added to the maximum values.
t
t
t
t
t
t
t
t
t
t
t
t
29
30
31
32
33
34
35
36
37
58
59
60
DD
Symbol
clock edge.
This adds even more time for deactivating READY. 2t
refers to the current bus cycle.
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
= 5 V ±10%,
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
Synchronous READY
setup time to CLKOUT
Synchronous READY
hold time after CLKOUT
Asynchronous READY
low time
Asynchronous READY
setup time
Asynchronous READY
hold time
Async. READY hold time
after RD, WR high
(Demultiplexed
Bus)
(2)
V
Parameter
SS
(1)
(1)
= 0 V
, T
A
= -40 to + 125 °C,
– 2 + t
Min.
25
10
17
35
17
9
–
2
2
0
F
TCL = 12.5 ns
CPU
A
= 40 MHz
A
2t
and t
A
C
8 + t
Max.
+ tC + t
L
25
C
–
4
–
= 50 pF
refer to the next following bus cycle and t
A
F
2TCL + 10
TCL – 3.5
TCL – 2.5
1/2 TCL = 1 to 64 MHz
– 2 + t
2TCL
Variable CPU clock
Min.
17
17
–
2
2
0
A
2t
A
2TCL
8 + t
Max.
+ tC + t
ST10F276Z5
–
4
–
A
F
F
ns