ST10F276Z5Q3 STMicroelectronics, ST10F276Z5Q3 Datasheet - Page 224
![MCU 16BIT 832KB FLASH 144-PQFP](/photos/12/15/121566/497-144-pqfp_series_sml.jpg)
ST10F276Z5Q3
Manufacturer Part Number
ST10F276Z5Q3
Description
MCU 16BIT 832KB FLASH 144-PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F276Z5T3.pdf
(239 pages)
Specifications of ST10F276Z5Q3
Core Processor
ST10
Core Size
16-Bit
Speed
64MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
832KB (832K x 8)
Program Memory Type
FLASH
Ram Size
68K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-QFP
Processor Series
ST10F27x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
68 KB
Interface Type
CAN/I2C
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
111
Number Of Timers
5
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
24-ch x 10-bit
For Use With
497-6399 - KIT DEV STARTER ST10F276Z5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-5580
Available stocks
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Manufacturer
Quantity
Price
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Electrical characteristics
23.8.22
224/239
High-speed synchronous serial interface (SSC) timing modes
Master mode
V
Table 110. Master mode
1. Maximum baud rate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and <SSCBR> set to
2. Formula for SSC Clock Cycle time:
t
t
t
t
t
t
t
t
t
t
t
300
301
302
303
304
305
306
307p
308p
307
308
DD
Symbol
‘3h’, or with 48 MHz CPU clock and <SSCBR> set to ‘2h’. When 40 MHz CPU clock is used the maximum
baud rate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>.
Value ‘1h’ for <SSCBR> may be used only with CPU clock equal to (or lower than) 32 MHz (after checking
that timings are in line with the target slave).
t
Where <SSCBR> represents the content of the SSC baud rate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t
300
= 5 V ±10%, V
= 4 TCL x (<SSCBR> + 1)
CC
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SSC clock cycle time
SSC clock high time
SSC clock low time
SSC clock rise time
SSC clock fall time
Write data valid after shift
edge
Write data hold after shift
edge
Read data setup time
before latch edge, phase
error detection on
(SSCPEN = 1)
Read data hold time after
latch edge, phase error
detection on (SSCPEN = 1)
Read data setup time
before latch edge, phase
error detection off
(SSCPEN = 0)
Read data hold time after
latch edge, phase error
detection off (SSCPEN = 0)
3
SS
Parameter
= 0 V, T
300
is 125 ns (corresponding to 8Mbaud)
A
(2)
= -40 to +125 °C, C
(<SSCBR> = 0002h)
6.6MBd
Min.
37.5
150
– 2
Max. baud rate
63
50
25
–
0
40 MHz
(1)
@F
L
= 50 pF
Max.
CPU
150
10
15
–
–
=
2TCL + 12.5
t
300
(<SSCBR> = 0001h -
8TCL
4TCL
2TCL
Variable baud rate
Min.
/ 2 – 12
– 2
–
0
FFFFh)
262144 TCL
Max.
ST10F276Z5
10
15
–
–
Unit
ns
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