MC9S08QG8CDNE Freescale Semiconductor, MC9S08QG8CDNE Datasheet - Page 170
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MC9S08QG8CDNE
Manufacturer Part Number
MC9S08QG8CDNE
Description
IC MCU 8K FLASH 8MHZ 8-SOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08QG8CDTER.pdf
(314 pages)
Specifications of MC9S08QG8CDNE
Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
4
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
S08QG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08QG8E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Inter-Integrated Circuit (S08IICV1)
11.4.1.8
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
11.4.1.9
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it. If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
11.5
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
11.6
The IIC generates a single interrupt.
An interrupt from the IIC is generated when any of the events in
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a one to it in the interrupt routine.
The user can determine the interrupt type by reading the status register.
168
Resets
Interrupts
SCL1
SCL2
SCL
Handshaking
Clock Stretching
Match of received calling address
Complete 1-byte transfer
Interrupt Source
INTERNAL COUNTER RESET
Arbitration Lost
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Figure 11-9. IIC Clock Synchronization
Table 11-8. Interrupt Summary
DELAY
Status
ARBL
IAAS
TCF
IICIF
IICIF
IICIF
Table 11-8
Flag
START COUNTING HIGH PERIOD
Local Enable
occur provided the IICIE bit
IICIE
IICIE
IICIE
Freescale Semiconductor
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