MC9S08QG8CDNE Freescale Semiconductor, MC9S08QG8CDNE Datasheet - Page 241
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MC9S08QG8CDNE
Manufacturer Part Number
MC9S08QG8CDNE
Description
IC MCU 8K FLASH 8MHZ 8-SOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08QG8CDTER.pdf
(314 pages)
Specifications of MC9S08QG8CDNE
Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
4
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
S08QG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08QG8E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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16.4.2.2
With the output compare function, the TPM can generate timed pulses with programmable position,
polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an
output compare channel, the TPM can set, clear, or toggle the channel pin.
In output compare mode, values are transferred to the corresponding timer channel value registers only
after both 8-bit bytes of a 16-bit register have been written. This coherency sequence can be manually reset
by writing to the channel status/control register (TPMCnSC).
An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.
16.4.2.3
This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS = 0) and can
be used when other channels in the same TPM are configured for input capture or output compare
functions. The period of this PWM signal is determined by the setting in the modulus register
(TPMMODH:TPMMODL). The duty cycle is determined by the setting in the timer channel value register
(TPMCnVH:TPMCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA
control bit. Duty cycle cases of 0 percent and 100 percent are possible.
As
(duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the
pulse width. If ELSnA = 0, the counter overflow forces the PWM signal high and the output compare
forces the PWM signal low. If ELSnA = 1, the counter overflow forces the PWM signal low and the output
compare forces the PWM signal high.
When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting the timer channel
value register (TPMCnVH:TPMCnVL) to a value greater than the modulus setting, 100% duty cycle can
be achieved. This implies that the modulus setting must be less than 0xFFFF to get 100% duty cycle.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to
ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register,
TPMCnVH or TPMCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the
corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and
the value in the TPMCNTH:TPMCNTL counter is 0x0000. (The new duty cycle does not take effect until
the next full period.)
Freescale Semiconductor
Figure 16-11
Output Compare Mode
Edge-Aligned PWM Mode
TPMCH
shows, the output compare value in the TPM channel registers determines the pulse width
OVERFLOW
Figure 16-11. PWM Period and Pulse Width (ELSnA = 0)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
PULSE
WIDTH
PERIOD
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
Timer/Pulse-Width Modulator (S08TPMV2)
COMPARE
OUTPUT
239
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