S9S08SG4E2CSC Freescale Semiconductor, S9S08SG4E2CSC Datasheet - Page 247
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S9S08SG4E2CSC
Manufacturer Part Number
S9S08SG4E2CSC
Description
MCU 4K FLASH 8-SOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG4E2CSC.pdf
(316 pages)
Specifications of S9S08SG4E2CSC
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
4
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
- 0.3 V to + 5.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
On-chip Dac
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register)
such that the buffer latches remain in the state they were in when the BDM became active, even if one or
both halves of the modulo register are written while BDM is active. Any write to the modulo registers
bypasses the buffer latches and directly writes to the modulo register while BDM is active.
Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first
counter overflow will occur.
16.3.4
TPMxCnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt
enable, channel configuration, and pin function.
Freescale Semiconductor
Reset
Reset
Reset
W
W
W
R
R
R
CHnF
Bit 15
Bit 7
TPM Channel n Status and Control Register (TPMxCnSC)
0
0
0
0
7
7
7
Figure 16-12. TPM Channel n Status and Control Register (TPMxCnSC)
= Unimplemented or Reserved
Figure 16-10. TPM Counter Modulo Register High (TPMxMODH)
Figure 16-11. TPM Counter Modulo Register Low (TPMxMODL)
CHnIE
14
0
6
0
0
6
6
6
MC9S08SG8 MCU Series Data Sheet, Rev. 6
MSnB
13
5
0
5
5
0
5
0
MSnA
12
0
4
0
0
4
4
4
ELSnB
11
0
3
0
0
3
3
3
Chapter 16 Timer/PWM Module (S08TPMV3)
ELSnA
10
0
2
0
0
2
2
2
1
9
0
1
1
0
1
0
0
Bit 8
Bit 0
0
0
0
0
0
0
0
247
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