S9S08SG16E1VTL Freescale Semiconductor, S9S08SG16E1VTL Datasheet - Page 134

• Manufacturer Part Number: S9S08SG16E1VTL
• Description: MCU 16K FLASH 28-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08SG16E1VTL

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-TSSOP
• Processor Series: S08SG
• Core: HCS08
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
134
ADLSMP
ADICLK
ADLPC
MODE
Field
ADIV
6:5
3:2
1:0
7
4
Reset:
W
R
Low-Power Configuration — ADLPC controls the speed and power configuration of the successive
approximation converter. This optimizes power consumption when higher sample rates are not required.
0 High speed configuration
1 Low power configuration: {FC31}The power is reduced at the expense of maximum clock speed.
Clock Divide Select — ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
Table 9-7
Long Sample Time Configuration — ADLSMP selects between long and short sample time. This adjusts the
sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time
Conversion Mode Selection — MODE bits select between 10- or 8-bit operation. See
Input Clock Select — ADICLK bits select the input clock source to generate the internal clock ADCK. See
Table
ADLPC
9-9.
7
0
shows the available clock configurations.
MODE
ADIV
00
01
10
11
00
01
10
11
0
6
Table 9-6. ADCCFG Register Field Descriptions
Figure 9-9. Configuration Register (ADCCFG)
ADIV
8-bit conversion (N=8)
Reserved
10-bit conversion (N=10)
Reserved
Table 9-7. Clock Divide Select
Table 9-8. Conversion Modes
MC9S08SG32 Data Sheet, Rev. 8
0
5
Divide Ratio
1
2
4
8
ADLSMP
0
4
Mode Description
Description
0
3
MODE
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
Clock Rate
Input clock
0
2
Freescale Semiconductor
0
1
Table
ADICLK
9-8.
0
0