C8051T630-GM Silicon Laboratories Inc, C8051T630-GM Datasheet - Page 104
![IC MCU 8KB 20PIN QFN](/photos/12/25/122567/silicon_laboratories_inc-20-qfn_sml.jpg)
C8051T630-GM
Manufacturer Part Number
C8051T630-GM
Description
IC MCU 8KB 20PIN QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T63xr
Specifications of C8051T630-GM
Program Memory Type
OTP
Program Memory Size
8KB (8K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T630DK
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1464 - KIT DEV FOR C8051T630 FAMILY
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1458-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051T630-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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- Download datasheet (2Mb)
C8051T630/1/2/3/4/5
SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control
SFR Address = 0xB2
104
Name
Reset
3:2
1:0
Bit
Type
7
6
5
4
Bit
SUSPEND
IFCN[1:0]
STSYNC
IOSCEN
Unused
IFRDY
IOSCEN
Name
R/W
7
1
Internal H-F Oscillator Enable Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
Internal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The inter-
nal oscillator resumes operation when one of the SUSPEND mode awakening
events occurs.
Suspend Timer Synchronization Bit.
This bit is used to indicate when it is safe to read and write the registers associated
with the suspend wake-up timer. If a suspend wake-up source other than the timer
has brought the oscillator out of suspend mode, it may take up to three timer clocks
before the timer can be read or written. When STSYNC reads '1', reads and writes of
the timer register should not be performed. When STSYNC reads '0', it is safe to
read and write the timer registers.
Unused. Read = 00b; Write = Don’t Care
Internal H-F Oscillator Frequency Divider Control Bits.
00: SYSCLK derived from Internal H-F Oscillator divided by 8.
01: SYSCLK derived from Internal H-F Oscillator divided by 4.
10: SYSCLK derived from Internal H-F Oscillator divided by 2.
11: SYSCLK derived from Internal H-F Oscillator divided by 1.
IFRDY
R
6
1
SUSPEND
R/W
5
0
STSYNC
Rev. 1.0
R
4
0
Function
R
3
0
R
2
0
1
0
IFCN[1:0]
R/W
0
0
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