C8051T630-GM Silicon Laboratories Inc, C8051T630-GM Datasheet - Page 7
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C8051T630-GM
Manufacturer Part Number
C8051T630-GM
Description
IC MCU 8KB 20PIN QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T63xr
Specifications of C8051T630-GM
Program Memory Type
OTP
Program Memory Size
8KB (8K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T630DK
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1464 - KIT DEV FOR C8051T630 FAMILY
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1458-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051T630-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
List of Figures
1. System Overview
3. Pin Definitions
4. QFN-20 Package Specifications
5. Electrical Characteristics
6. 10-Bit ADC (ADC0, C8051T630/2/4 only)
7. Temperature Sensor (C8051T630/2/4 only)
8. 10-Bit Current Mode DAC (IDA0, C8051T630/2/4 only)
9. Voltage Reference Options
11. Comparator0
12. CIP-51 Microcontroller
13. Memory Organization
18. Reset Sources
19. Oscillators and Clock Selection
20. Port Input/Output
Figure 1.1. C8051T630/1/2/3/4/5 Block Diagram .................................................... 16
Figure 3.1. QFN-20 Pinout Diagram (Top View) ..................................................... 20
Figure 4.1. QFN-20 Package Drawing .................................................................... 21
Figure 4.2. QFN-20 Recommended PCB Land Pattern .......................................... 22
Figure 5.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) ......... 32
Figure 5.2. Idle Mode Digital Supply Current vs. Frequency (MPCE = 1) ............... 32
Figure 6.1. ADC0 Functional Block Diagram ........................................................... 33
Figure 6.2. 10-Bit ADC Track and Conversion Example Timing ............................. 35
Figure 6.3. ADC0 Equivalent Input Circuits ............................................................. 36
Figure 6.4. ADC Window Compare Example: Right-Justified Data ......................... 42
Figure 6.5. ADC Window Compare Example: Left-Justified Data ........................... 42
Figure 6.6. ADC0 Multiplexer Block Diagram .......................................................... 43
Figure 7.1. Temperature Sensor Transfer Function ................................................ 45
Figure 7.2. Temperature Sensor Error with 1-Point Calibration at 0 Celsius ........... 46
Figure 8.1. IDA0 Functional Block Diagram ............................................................ 48
Figure 8.2. IDA0 Data Word Mapping ..................................................................... 49
Figure 9.1. Voltage Reference Functional Block Diagram ....................................... 53
Figure 11.1. Comparator0 Functional Block Diagram ............................................. 57
Figure 11.2. Comparator Hysteresis Plot ................................................................ 58
Figure 11.3. Comparator Input Multiplexer Block Diagram ...................................... 61
Figure 12.1. CIP-51 Block Diagram ......................................................................... 63
Figure 13.1. Memory Map ....................................................................................... 72
Figure 13.2. Program Memory Map ......................................................................... 73
Figure 18.1. Reset Sources ..................................................................................... 95
Figure 18.2. Power-On and VDD Monitor Reset Timing ......................................... 96
Figure 19.1. Oscillator Options .............................................................................. 101
Figure 20.1. Port I/O Functional Block Diagram .................................................... 109
Figure 20.2. Port I/O Cell Block Diagram .............................................................. 111
Figure 20.3. Crossbar Priority Decoder with No Pins Skipped .............................. 114
Rev. 1.0
C8051T630/1/2/3/4/5
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