C8051T630-GM Silicon Laboratories Inc, C8051T630-GM Datasheet - Page 118
C8051T630-GM
Manufacturer Part Number
C8051T630-GM
Description
IC MCU 8KB 20PIN QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T63xr
Specifications of C8051T630-GM
Program Memory Type
OTP
Program Memory Size
8KB (8K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T630DK
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1464 - KIT DEV FOR C8051T630 FAMILY
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1458-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051T630-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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C8051T630/1/2/3/4/5
SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1
SFR Address = 0xE2
20.5. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in the PnMATCH registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the soft-
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMATCH registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(P0MATCH & P0MASK) or if (P1 & P1MASK) does not equal (P1MATCH & P1MASK).
118
Name WEAKPUD
Reset
1:0 PCA0ME[1:0] PCA Module I/O Enable Bits.
Bit
Type
7
6
5
4
3
2
Bit
WEAKPUD
Unused
XBARE
Name
ECIE
T1E
T0E
R/W
7
0
Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
PCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
Unused. Read = 0b; Write = Don’t Care.
00: All PCA I/O unavailable at Port pins.
01: CEX0 routed to Port pin.
10: CEX0, CEX1 routed to Port pins.
11: CEX0, CEX1, CEX2 routed to Port pins.
XBARE
R/W
6
0
R/W
T1E
5
0
Rev. 1.0
T0E
R/W
4
0
Function
ECIE
R/W
3
0
R
2
0
R/W
PCA0ME[1:0]
1
0
R/W
0
0
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