C8051F521A-IM Silicon Laboratories Inc, C8051F521A-IM Datasheet - Page 109
![IC 8051 MCU 8K FLASH 10DFN](/photos/12/15/121585/10-dfn_pkg_sml.jpg)
C8051F521A-IM
Manufacturer Part Number
C8051F521A-IM
Description
IC 8051 MCU 8K FLASH 10DFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F52xr
Specifications of C8051F521A-IM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
10-DFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
6
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
6
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1488 - KIT DEV C8051F53XA, C8051F52XA770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1455 - ADAPTER PROGRAM TOOLSTICK F520
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1490-5
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SFR Definition 11.1. VDDMON: V
11.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 2.7 on page 32 for complete
RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
11.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise,
this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it.
The state of the RST pin is unaffected by this reset.
11.5. Comparator Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
Bit7:
Bit6:
Bit5:
Bits4–0: RESERVED. Read = Variable. Write = don’t care.
VDMEN VDDSTAT VDMLVL Reserved Reserved Reserved Reserved Reserved 1v000000
R/W
Bit7
VDMEN: V
This bit turns the V
resets until it is also selected as a reset source in register RSTSRC (SFR Definition 11.2).
The V
ing the V
reset. See Table 2.7 on page 32 for the minimum V
0: V
1: V
VDDSTAT: V
This bit indicates the current power supply status (V
0: V
1: V
VDMLVL: V
0: V
1: V
includes code that writes to and/or erases Flash.
DD
DD
DD
DD
DD
DD
Bit6
DD
R
Monitor Disabled.
Monitor Enabled (default).
is at or below the V
is above the V
Monitor Threshold is set to V
Monitor Threshold is set to V
Monitor can be allowed to stabilize before it is selected as a reset source. Select-
DD
DD
DD
monitor as a reset source before it has stabilized may generate a system
DD
Monitor Enable.
Level Select.
Status.
R/W
Bit5
DD
DD
monitor circuit on/off. The V
Monitor Threshold.
DD
Bit4
C8051F52x/F52xA/F53x/F53xA
R
Monitor Threshold.
DD
Monitor Control
RST-LOW
RST-HIGH
Rev. 1.3
Bit3
R
. This setting is required for any system that
(default).
DD
Bit2
R
DD
DD
Monitor cannot generate system
Monitor turn-on time.
Monitor output).
Bit1
R
SFR Address:
Bit0
R
Reset Value
0xFF
109
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