MCR908JL3ECFAE Freescale Semiconductor, MCR908JL3ECFAE Datasheet - Page 100
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MCR908JL3ECFAE
Manufacturer Part Number
MCR908JL3ECFAE
Description
IC MCU 4K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JK1ECDWE.pdf
(180 pages)
Specifications of MCR908JL3ECFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
23
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCR908JL3ECFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Analog-to-Digital Converter (ADC)
9.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the
analog circuitry before attempting a new ADC conversion after exiting stop mode.
9.6 I/O Signals
The ADC module has 12 channels that are shared with I/O port B and port D.
9.6.1 ADC Voltage In (ADCVIN)
ADCVIN is the input voltage signal from one of the 12 ADC channels to the ADC module.
9.7 I/O Registers
These I/O registers control and monitor ADC operation:
9.7.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and control register.
COCO — Conversions Complete Bit
AIEN — ADC Interrupt Enable Bit
100
•
•
•
When the AIEN bit is a 0, the COCO is a read-only bit which is set each time a conversion is completed.
This bit is cleared whenever the ADC status and control register is written or whenever the ADC data
register is read. Reset clears this bit.
When the AIEN bit is a 1 (CPU interrupt enabled), the COCO is a read-only bit, and will always be 0
when read.
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADC status and control register (ADSCR)
ADC data register (ADR)
ADC clock register (ADICLK)
Address:
Reset:
Read:
Write:
$003C
COCO
Figure 9-3. ADC Status and Control Register (ADSCR)
Bit 7
0
= Unimplemented
AIEN
MC68HC908JL3E Family Data Sheet, Rev. 4
6
0
ADCO
5
0
ADCH4
4
1
ADCH3
3
1
ADCH2
2
1
ADCH1
1
1
Freescale Semiconductor
ADCH0
Bit 0
1
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