MCR908JL3ECFAE Freescale Semiconductor, MCR908JL3ECFAE Datasheet - Page 101
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MCR908JL3ECFAE
Manufacturer Part Number
MCR908JL3ECFAE
Description
IC MCU 4K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JK1ECDWE.pdf
(180 pages)
Specifications of MCR908JL3ECFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
23
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCR908JL3ECFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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ADCO — ADC Continuous Conversion Bit
ADCH[4:0] — ADC Channel Select Bits
Freescale Semiconductor
When set, the ADC will convert samples continuously and update the ADR register at the end of each
conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels. The five channel select
bits are detailed in the following table. Care should be taken when using a port pin as both an analog
and a digital input simultaneously to prevent switching noise from corrupting the analog signal.
The ADC subsystem is turned off when the channel select bits are all set to one. This feature allows
for reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to
a 1.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH4
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the
operation of the ADC converter both in production test and for user applications.
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
:
Recovery from the disabled state requires one conversion cycle to stabilize.
ADCH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
:
ADCH2
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
1
1
:
MC68HC908JL3E Family Data Sheet, Rev. 4
Table 9-1. MUX Channel Select
ADCH1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
:
NOTE
ADCH0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
:
ADC Channel
ADC10
ADC11
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
—
—
—
ADC power off
Input Select
(see Note 1)
(see Note 2)
(see Note 2)
Reserved
Unused
Unused
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
PTD3
PTD2
PTD1
PTD0
V
V
DDA
SSA
I/O Registers
101
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