MC68908GZ8VFAE Freescale Semiconductor, MC68908GZ8VFAE Datasheet - Page 273
![IC MCU 8BIT 8K FLASH 48-LQFP](/photos/37/62/376278/tqfp-48_sml.jpg)
MC68908GZ8VFAE
Manufacturer Part Number
MC68908GZ8VFAE
Description
IC MCU 8BIT 8K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68908GZ8VFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
ESCI, SPI, UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68908GZ8VFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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When the internal address bus matches the value written in the break address registers or when software
writes a logic 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by:
The break interrupt timing is:
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
A break address should be placed at the address of the instruction opcode. When software does not
change the break address and clears the BRKA bit in the first break interrupt routine, the next break
interrupt will not be generated after exiting the interrupt routine even when the internal address bus
matches the value written in the break address registers.
20.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See
for each module.
20.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
20.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt when V
20.2.2 Break Module Registers
These registers control and monitor operation of the break module:
Freescale Semiconductor
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Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
When a break address is placed at an address of an instruction operand, the instruction is executed
before the break interrupt.
When software writes a logic 1 to the BRKA bit, the break interrupt occurs just before the next
instruction is executed.
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
Break status register (BSR)
Break flag control register (BFCR)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
16.7.3 Break Flag Control Register
CAUTION
TST
is present on the RST pin.
and the Break Interrupts subsection
Break Module (BRK)
273
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