MC9S08RD32PE Freescale Semiconductor, MC9S08RD32PE Datasheet - Page 68

• Manufacturer Part Number: MC9S08RD32PE
• Description: IC MCU 32K FLASH 2K RAM 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32PE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: S08RD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08RG60E
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Resets, Interrupts, and System Configuration
5.8.4
This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a
write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT
must be written during the user’s reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
68
BKGDPE
STOPE
RSTPE
COPE
COPT
Field
7
6
5
1
0
Reset
W
R
System Options Register (SOPT)
COP Watchdog Enable — This write-once bit defaults to 1 after reset.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
COP Watchdog Timeout — This write-once bit defaults to 1 after reset.
0 Short timeout period selected (2
1 Long timeout period selected (2
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
Background Debug Mode Pin Enable — The BKGDPE bit enables the PTD0/BKGD/MS pin to function as
BKGD/MS. When the bit is clear, the pin will function as PTD0, which is an output only general purpose I/O. This
pin always defaults to BKGD/MS function after any reset.
0 BKGD pin disabled.
1 BKGD pin enabled.
RESET Pin Enable — The RSTPE bit enables the PTD1/RESET pin to function as RESET. When the bit is clear,
the pin will function as PTD1, which is an output only general purpose I/O. This pin always defaults to RESET
function after any reset.
0 RESET pin disabled.
1 RESET pin enabled.
COPE
1
7
= Unimplemented or Reserved
COPT
6
1
Figure 5-5. System Options Register (SOPT)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Table 5-5. SOPT Field Descriptions
STOPE
0
5
20
18
cycles of BUSCLK).
cycles of BUSCLK).
4
1
Description
0
0
3
2
0
0
BKGDPE
Freescale Semiconductor
1
1
RSTPE
0
1