R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet - Page 26

• Manufacturer Part Number: R5F211B1SP#U0
• Description: IC R8C MCU FLASH 4K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/1Br

Specifications of R5F211B1SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K5211B4S001BE - KIT STARTER FOR R8C/18191A1BR0K5211B4S000BE - KIT DEV EVALUATION R8C/1BR0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
1.4 Flag Register (FLG)
Chapter 1 Overview
Figure 1.4.1 shows the configuration of the flag register (FLG). The function of each flag is described
below.
1.4.1 Bit 0: Carry Flag (C Flag)
1.4.2 Bit 1: Debug Flag (D Flag)
1.4.3 Bit 2: Zero Flag (Z Flag)
1.4.4 Bit 3: Sign Flag (S Flag)
1.4.5 Bit 4: Register Bank Select Flag (B Flag)
1.4.6 Bit 5: Overflow Flag (O Flag)
1.4.7 Bit 6: Interrupt Enable Flag (I Flag)
1.4.8 Bit 7: Stack Pointer Select Flag (U Flag)
1.4.9 Bits 8 to 11: Reserved
This flag holds bits carried, borrowed, or shifted-out by the arithmetic/logic unit.
This flag enables a single-step interrupt.
When this flag is set to 1, a single-step interrupt is generated after an instruction is executed. When the
interrupt is acknowledged, the flag is cleared to 0.
This flag is set to 1 when an arithmetic operation results in 0; otherwise, its value is 0.
This flag is set to 1 when an arithmetic operation results in a negative value; otherwise, its value is 0.
This flag selects a register bank. If it is set to 0, register bank 0 is selected; if it is set to 1, register bank
1 is selected.
This flag is set to 1 when an arithmetic operation results in an overflow.
This flag enables a maskable interrupt.
When this flag is set to 0, the interrupt is disabled; when it is set to 1, the interrupt is enabled. When the
interrupt is acknowledged, the flag is cleared to 0.
When this flag is set to 0, the interrupt stack pointer (ISP) is selected; when it is set to 1, the user stack
pointer (USP) is selected.
This flag is cleared to 0 when a hardware interrupt is acknowledged or an INT instruction is executed for
software interrupt numbers 0 to 31.
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1.4 Flag Register (FLG)