R5F211B1SP#U0 Renesas Electronics America, R5F211B1SP#U0 Datasheet
R5F211B1SP#U0
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R5F211B1SP#U0 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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R8C/1A Group, 16 R8C/1B Group Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER R8C FAMILY / R8C/1x SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating ...
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Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in ...
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Register Notation The symbols and terms used in register diagrams are described below. XXX Register Bit Symbol XXX0 XXX1 XXX4 XXX5 XXX6 XXX7 *1 Blank: Set ...
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List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct ...
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SFR Page Reference 1. Overview 1.1 Applications .................................................................................................1 1.2 Performance Overview................................................................................2 1.3 Block Diagram .............................................................................................4 1.4 Product Information .....................................................................................5 1.5 Pin Assignments..........................................................................................9 1.6 Pin Functions.............................................................................................12 2. Central Processing Unit (CPU) 2.1 Data Registers (R0, R1, R2, and R3)........................................................16 2.2 Address ...
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Special Function Registers (SFRs) 5. Programmable I/O Ports 5.1 Functions of Programmable I/O Ports .......................................................24 5.2 Effect on Peripheral Functions ..................................................................24 5.3 Pins Other than Programmable I/O Ports..................................................24 5.4 Port Settings..............................................................................................32 5.5 Unassigned Pin Handling ..........................................................................37 6. Resets 6.1 ...
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CPU Clock and Peripheral Function Clock................................................67 10.3.1 System Clock......................................................................................67 10.3.2 CPU Clock ..........................................................................................67 10.3.3 Peripheral Function Clock (f1, f2, f4, f8, f32) ......................................67 10.3.4 fRING and fRING128..........................................................................67 10.3.5 fRING-fast...........................................................................................67 10.3.6 fRING-S ..............................................................................................67 10.4 Power Control............................................................................................68 10.4.1 Standard Operating Mode ...
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Address Match Interrupt ............................................................................98 12.5 Notes on Interrupts..................................................................................100 12.5.1 Reading Address 00000h .................................................................100 12.5.2 SP Setting.........................................................................................100 12.5.3 External Interrupt and Key Input Interrupt ........................................100 12.5.4 Watchdog Timer Interrupt.................................................................100 12.5.5 Changing Interrupt Sources..............................................................101 12.5.6 Changing Interrupt Control Register Contents .................................102 ...
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Continuous Receive Mode ...............................................................162 15.2 Clock Asynchronous Serial I/O (UART) Mode ........................................163 15.2.1 CNTR0 Pin Select Function..............................................................166 15.2.2 Bit Rate.............................................................................................167 15.3 Notes on Serial Interface.........................................................................168 16. Clock Synchronous Serial Interface 16.1 Mode Selection........................................................................................169 16.2 Clock Synchronous Serial I/O with ...
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Flash Memory 18.1 Overview .................................................................................................245 18.2 Memory Map ...........................................................................................247 18.3 Functions to Prevent Rewriting of Flash Memory....................................249 18.3.1 ID Code Check Function ..................................................................249 18.3.2 ROM Code Protect Function ............................................................250 18.4 CPU Rewrite Mode..................................................................................251 18.4.1 EW0 Mode........................................................................................252 18.4.2 EW1 Mode........................................................................................252 ...
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Notes on Timer X..............................................................................300 20.3.2 Notes on Timer Z..............................................................................300 20.3.3 Notes on Timer C .............................................................................301 20.4 Notes on Serial Interface.........................................................................302 20.5 Precautions on Clock Synchronous Serial Interface ...............................303 20.5.1 Notes on Clock Synchronous Serial I/O with Chip Select ................303 ...
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SFR Page Reference Address Register 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0006h System Clock Control Register 0 0007h System Clock Control Register 1 0008h 0009h Address Match Interrupt Enable Register 000Ah Protect ...
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Address Register 0080h Timer Z Mode Register 0081h 0082h 0083h 0084h Timer Z Waveform Output Control Register 0085h Prescaler Z Register 0086h Timer Z Secondary Register 0087h Timer Z Primary Register 0088h 0089h 008Ah Timer Z Output Control Register 008Bh ...
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R8C/1A Group, R8C/1B Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. Overview These MCUs are fabricated using the high-performance silicon gate CMOS process, embedding the R8C/ Tiny Series CPU core, and is packaged in a 20-pin molded-plastic LSSOP, SDIP or a 28-pin ...
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R8C/1A Group, R8C/1B Group 1.2 Performance Overview Table 1.1 outlines the Functions and Specifications for R8C/1A Group and Table 1.2 outlines the Functions and Specifications for R8C/1B Group. Table 1.1 Functions and Specifications for R8C/1A Group Item CPU Number of ...
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R8C/1A Group, R8C/1B Group Table 1.2 Functions and Specifications for R8C/1B Group Item CPU Number of fundamental instructions Minimum instruction execution time Operating mode Address space Memory capacity Peripheral Ports Functions LED drive ports Timers Serial interfaces Clock synchronous serial ...
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R8C/1A Group, R8C/1B Group 1.3 Block Diagram Figure 1.1 shows a Block Diagram. I/O ports Peripheral Functions Timers Timer X (8 bits) Timer Z (8 bits) Timer C (16 bits) Watchdog timer (15 bits) Figure 1.1 Block Diagram Rev.1.30 Dec ...
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R8C/1A Group, R8C/1B Group 1.4 Product Information Table 1.3 lists Product Information for R8C/1A Group and Table 1.4 lists Product Information for R8C/1B Group. Table 1.3 Product Information for R8C/1A Group Type No. ROM Capacity R5F211A1SP 4 Kbytes R5F211A2SP 8 ...
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R8C/1A Group, R8C/1B Group Type No XXX SP NOTE: Please contact Renesas Technology sales offices for the Y version. Figure 1.2 Type Number, Memory Size, and Package of R8C/1A Group Rev.1.30 Dec 08, ...
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R8C/1A Group, R8C/1B Group Table 1.4 Product Information for R8C/1B Group Type No. Program ROM R5F211B1SP 4 Kbytes R5F211B2SP 8 Kbytes R5F211B3SP 12 Kbytes R5F211B4SP 16 Kbytes R5F211B1DSP 4 Kbytes R5F211B2DSP 8 Kbytes R5F211B3DSP 12 Kbytes R5F211B4DSP 16 Kbytes R5F211B1DD ...
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R8C/1A Group, R8C/1B Group Type No XXX SP NOTE: Please contact Renesas Technology sales offices for the Y version. Figure 1.3 Type Number, Memory Size, and Package of R8C/1B Group Rev.1.30 Dec 08, ...
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R8C/1A Group, R8C/1B Group 1.5 Pin Assignments Figure 1.4 shows Pin Assignments for PLSP0020JB-A Package (Top View), Figure 1.5 shows Pin Assignments for PRDP0020BA-A Package (Top View) and Figure 1.6 shows Pin Assignments for PWQN0028KA-B Package (Top View). PIN assignments ...
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R8C/1A Group, R8C/1B Group PIN assignments (top view) P3_5/SSCK/SCL/CMP1_2 P3_7/CNTR0/SSO/TXD1 RESET XOUT/P4_7 VSS/AVSS XIN/P4_6 VCC/AVCC MODE P4_5/INT0/RXD1 P1_7/CNTR00/INT10 Figure 1.5 Pin Assignments for PRDP0020BA-A Package (Top View) Rev.1.30 Dec 08, 2006 Page 10 of 315 REJ09B0252-0130 ...
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R8C/1A Group, R8C/1B Group PIN Assignment (top view) P1_1/AN9/KI1/CMP0_1 P1_0/AN8/KI0/CMP0_0 P3_3/TCIN/INT3/SSI00/CMP1_0 P3_4/SCS/SDA/CMP1_1 P3_5/SSCK/SCL/CMP1_2 P3_7/CNTR0/SSO/TXD1 RESET Figure 1.6 Pin Assignments for PWQN0028KA-B Package (Top View) Rev.1.30 Dec 08, 2006 Page 11 of 315 REJ09B0252-0130 ...
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R8C/1A Group, R8C/1B Group 1.6 Pin Functions Table 1.5 lists Pin Functions, Table 1.6 lists Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A Packages and Table 1.7 lists Pin Name Information by Pin Number of PWQN0028KA- B Package. Table ...
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R8C/1A Group, R8C/1B Group Table 1.6 Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A Packages Pin Control Port Number Pin 1 P3_5 2 P3_7 3 RESET 4 XOUT P4_7 5 VSS/AVSS 6 XIN P4_6 7 VCC/AVCC 8 MODE 9 ...
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R8C/1A Group, R8C/1B Group Table 1.7 Pin Name Information by Pin Number of PWQN0028KA-B Package Pin Control Port Number Pin XOUT P4_7 3 VSS/AVSS XIN P4_6 VCC/AVCC 9 MODE ...
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R8C/1A Group, R8C/1B Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 ...
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R8C/1A Group, R8C/1B Group 2.1 Data Registers (R0, R1, R2, and R3 16-bit register for transfer, arithmetic, and logic operations. The same applies R3. R0 can be split into high-order bits (R0H) and low-order ...
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R8C/1A Group, R8C/1B Group 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag ...
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R8C/1A Group, R8C/1B Group 3. Memory 3.1 R8C/1A Group Figure 3 Memory Map of R8C/1A Group. The R8C/1A Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning ...
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R8C/1A Group, R8C/1B Group 3.2 R8C/1B Group Figure 3 Memory Map of R8C/1B Group. The R8C/1B Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning ...
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R8C/1A Group, R8C/1B Group 4. Special Function Registers (SFRs) An SFR (special function register control register for a peripheral function. Tables 4.1 to 4.4 list the special function registers. Table 4.1 SFR Information (1) Address 0000h 0001h 0002h ...
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R8C/1A Group, R8C/1B Group Table 4.2 SFR Information (2) Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh Key Input Interrupt Control Register 004Eh A/D Conversion Interrupt Control Register 004Fh SSU/IIC Interrupt Control Register ...
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R8C/1A Group, R8C/1B Group Table 4.3 SFR Information (3) Address 0080h Timer Z Mode Register 0081h 0082h 0083h 0084h Timer Z Waveform Output Control Register 0085h Prescaler Z Register 0086h Timer Z Secondary Register 0087h Timer Z Primary Register 0088h ...
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R8C/1A Group, R8C/1B Group Table 4.4 SFR Information (4) Address 00C0h A/D Register 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Control Register 2 00D5h 00D6h A/D ...
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R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports There are 13 programmable Input/Output ports (I/O ports) P1, P3_3 to P3_5, P3_7, and P4_5. 4_2 can be used as an input-only port. Also, P4_6 and P4_7 can be used as input-only ...
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R8C/1A Group, R8C/1B Group P1_0 to P1_3 Direction register Output from individual peripheral function Data bus Port latch Input to individual peripheral function P1_4 Direction register Output from individual peripheral function Data bus Port latch P1_5 Direction register Data bus ...
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R8C/1A Group, R8C/1B Group P1_6, P1_7 Direction register Output from individual peripheral function Data bus Port latch Input to individual peripheral function P3_3 Output from individual peripheral function Data bus Input to individual peripheral function P3_4, P3_5, P3_7 Output from ...
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R8C/1A Group, R8C/1B Group P4_2 Vref of A/D converter P4_5 Data bus Input to individual peripheral function P4_6/XIN P4_7/XOUT NOTES: 1. When CM05 = 1, CM10 = 1, or CM13 = 0, the clocked inverter is cut off. 2. When ...
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R8C/1A Group, R8C/1B Group MODE MODE signal input RESET RESET signal input NOTE : 1. Ensure the input voltage to each port will not exceed VCC. Figure 5.4 Configuration of I/O Pins Rev.1.30 Dec 08, 2006 Page 28 of 315 ...
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R8C/1A Group, R8C/1B Group Port Pi Direction Register ( Symbol PD1 PD3 PD4 Bit Symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 NOTES : 1. Bits PD3_0 ...
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R8C/1A Group, R8C/1B Group Port P4 Register Symbol P4 Bit Symbol — (b1-b0) P4_2 — (b4-b3) P4_5 P4_6 P4_7 Figure 5.7 P4 Register Port Mode Register ...
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R8C/1A Group, R8C/1B Group Pull-Up Control Register Symbol PUR0 Bit Symbol (b1-b0) PU02 PU03 — (b5-b4) PU06 PU07 NOTE : 1. When this bit is set to 1 (pulled ...
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R8C/1A Group, R8C/1B Group 5.4 Port Settings Tables 5.4 to 5.17 list the port settings. Table 5.4 Port P1_0/KI0/AN8/CMP0_0 Register PD1 PUR0 DRR Bit PD1_0 PU02 DRR0 Setting ...
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R8C/1A Group, R8C/1B Group Table 5.7 Port P1_3/KI3/AN11/TZOUT Register PD1 PUR0 Bit PD1_3 PU02 Setting Value ...
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R8C/1A Group, R8C/1B Group Table 5.10 Port P1_6/CLK0/SSI01 Register PD1 PUR0 Bit PD1_6 PU03 0 0 Other than 0X10b 0 1 Other than 0X10b 0 0 Setting 1 X Other than 0X10b Value ...
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R8C/1A Group, R8C/1B Group Table 5.13 Port P3_4/SCS/SDA/CMP1_1 Register PD3 PUR0 Bit PD3_4 PU07 Setting Value Table 5.14 Port P3_5/SSCK/SCL/CMP1_2 ...
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R8C/1A Group, R8C/1B Group Table 5.15 Port P3_7/CNTR0/SSO/TXD1 Register PD3 PUR0 Bit PD3_7 PU07 Setting X X Value Table 5.16 Port XIN/P4_6, XOUT/P4_7 Register ...
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R8C/1A Group, R8C/1B Group 5.5 Unassigned Pin Handling Table 5.18 lists Unassigned Pin Handling. Figure 5.11 shows Unassigned Pin Handling. Table 5.18 Unassigned Pin Handling Pin Name Ports P1, P3_3 to P3_5, P3_7, P4_5 Ports P4_6, P4_7 Port P4_2/VREF (3) ...
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R8C/1A Group, R8C/1B Group 6. Resets The following resets are implemented: hardware reset, power-on reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, and software reset. Table 6.1 lists the Reset Names and Sources. Table 6.1 Reset ...
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R8C/1A Group, R8C/1B Group Table 6.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 6.2 shows CPU Register Status after Reset and Figure 6.3 shows Reset Sequence. Table 6.2 Pin Functions while RESET Pin Level is “L” ...
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R8C/1A Group, R8C/1B Group 6.1 Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, pins, CPU, and SFRs are reset ...
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R8C/1A Group, R8C/1B Group VCC RESET Figure 6.4 Example of Hardware Reset Circuit and Operation RESET Figure 6.5 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation Rev.1.30 Dec 08, 2006 Page 41 of ...
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R8C/1A Group, R8C/1B Group 6.2 Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor of about 5 kΩ, and the VCC pin voltage level rises, the power-on reset function is enabled and ...
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R8C/1A Group, R8C/1B Group 6.3 Voltage Monitor 1 Reset A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet1. When ...
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R8C/1A Group, R8C/1B Group 7. Voltage Detection Circuit The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program. Alternately, voltage monitor 1 reset, voltage ...
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R8C/1A Group, R8C/1B Group VCC Internal reference voltage Figure 7.1 Block Diagram of Voltage Detection Circuit Voltage detection 1 circuit VCA26 VCC + Internal - reference voltage Voltage detection 1 signal is held “H” when VCA26 bit is set to ...
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R8C/1A Group, R8C/1B Group Voltage detection 2 circuit fRING-S VCA27 VCA13 VCC + Noise filter Voltage Internal - detection reference 2 signal (Filter width: 200 ns) voltage Voltage detection 2 signal is held “H” when VCA27 bit is set to ...
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R8C/1A Group, R8C/1B Group Voltage Detection Register Symbol VCA1 Bit Symbol — (b2-b0) VCA13 — (b7-b4) NOTES : 1. The VCA13 bit is enabled ...
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R8C/1A Group, R8C/1B Group Voltage Monitor 1 Circuit Control Register Symbol VW1C Bit Symbol VW1C0 VW1C1 VW1C2 — (b3) VW1F0 VW1F1 VW1C6 VW1C7 NOTES : 1. Set the PRC3 bit in ...
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R8C/1A Group, R8C/1B Group Voltage Monitor 2 Circuit Control Register Symbol VW2C Bit Symbol VW2C0 VW2C1 VW2C2 VW2C3 VW2F0 VW2F1 VW2C6 VW2C7 NOTES : 1. Set the PRC3 bit in the PRCR ...
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R8C/1A Group, R8C/1B Group 7.1 VCC Input Voltage 7.1.1 Monitoring Vdet1 Vdet1 cannot be monitored. 7.1.2 Monitoring Vdet2 Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed (refer to 19. ...
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R8C/1A Group, R8C/1B Group Voltage monitor 1 reset VCC Vdet1 Sampling timing Internal reset signal Operation when the VW1C1 bit in the VW1C register is set to 0 (digital filter enabled) Voltage monitor 2 interrupt VCC Vdet2 Sampling timing Sampling ...
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R8C/1A Group, R8C/1B Group 7.2 Voltage Monitor 1 Reset Table 7.2 lists the Setting Procedure of Voltage Monitor 1 Reset Associated Bits and Figure 7.8 shows an Operating Example of Voltage Monitor 1 Reset. To use voltage monitor 1 reset ...
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R8C/1A Group, R8C/1B Group 7.3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 7.3 lists the Setting Procedure of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Associated Bits. Figure 7.9 shows an Operating Example of Voltage ...
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R8C/1A Group, R8C/1B Group Vdet2 (Typ. 3.30 V) (1) 2.7 V VCA13 bit VW2C2 bit When the VW2C1 bit is set to 0 (digital filter enabled). Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1) ...
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R8C/1A Group, R8C/1B Group 8. Processor Mode 8.1 Processor Modes Single-chip mode can be selected as the processor mode. Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1 Register. Table ...
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R8C/1A Group, R8C/1B Group (1) Processor Mode Register Symbol PM1 Bit Symbol — (b0) — (b1) PM12 — (b6-b3) — (b7) NOTES : 1. Set the PRC1 bit in ...
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R8C/1A Group, R8C/1B Group 9. Bus The bus cycles differ when accessing ROM/RAM, and when accessing SFR. Table 9.1 lists Bus Cycles by Access Space of the R8C/1A Group and Table 9.2 lists Bus Cycles by Access Space of the ...
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R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit The clock generation circuit has: • Main clock oscillation circuit • On-chip oscillator (oscillation stop detection function) Table 10.1 lists Specifications of Clock Generation Circuit. Figure 10.1 shows a Clock Generation Circuit. ...
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R8C/1A Group, R8C/1B Group S Q CM10 = 1(Stop mode) R RESET Power-on reset Software reset S Q Interrupt request WAIT R instruction CM13 XIN XOUT CM13 CM05 CM02, CM05, CM06: Bits in CM0 register CM10, CM13, CM14, CM16, CM17: ...
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R8C/1A Group, R8C/1B Group System Clock Control Register Symbol CM0 Bit Symbol — (b1-b0) CM02 — (b3) — (b4) CM05 CM06 — (b7) NOTES : 1. ...
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R8C/1A Group, R8C/1B Group System Clock Control Register Symbol CM1 Bit Symbol CM10 — (b1) — (b2) CM13 CM14 CM15 CM16 CM17 NOTES : 1. Set the PRC0 bit ...
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R8C/1A Group, R8C/1B Group Oscillation Stop Detection Register Symbol OCD Bit Symbol OCD0 OCD1 OCD2 OCD3 — (b7-b4) NOTES : 1. Set the PRC0 bit in the PRCR ...
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R8C/1A Group, R8C/1B Group High-Speed On-Chip Oscillator Control Register Symbol HRA0 Bit Symbol HRA00 HRA01 — (b7-b2) NOTES : 1. Set the PRC0 bit in ...
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R8C/1A Group, R8C/1B Group High-Speed On-Chip Oscillator Control Register Symbol HRA1 The frequency of the high-speed on-chip oscillator is adjusted w ith bits High-speed on-chip oscillator frequency = ...
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R8C/1A Group, R8C/1B Group The clocks generated by the clock generation circuits are described below. 10.1 Main Clock This clock is supplied by a main clock oscillation circuit. This clock is used as the clock source for the CPU and ...
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R8C/1A Group, R8C/1B Group 10.2 On-Chip Oscillator Clocks These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip oscillator). The on-chip oscillator clock is selected by the HRA01 bit in the HRA0 register. 10.2.1 Low-Speed ...
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R8C/1A Group, R8C/1B Group 10.3 CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 10.1 Clock Generation Circuit. 10.3.1 System Clock ...
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R8C/1A Group, R8C/1B Group 10.4 Power Control There are three power control modes. All modes other than wait mode and stop mode are referred to as standard operating mode. 10.4.1 Standard Operating Mode Standard operating mode is further separated into ...
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R8C/1A Group, R8C/1B Group 10.4.1.1 High-Speed Mode The main clock divided by 1 (no division) provides the CPU clock. If the CM14 bit is set to 0 (low-speed on- chip oscillator on) or the HRA00 bit in the HRA0 register ...
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R8C/1A Group, R8C/1B Group 10.4.2.4 Exiting Wait Mode The MCU exits wait mode by a hardware reset or a peripheral function interrupt. To use a hardware reset to exit wait mode, set bits ILVL2 to ILVL0 for the peripheral function ...
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R8C/1A Group, R8C/1B Group Figure 10.8 shows the Time from Wait Mode to Interrupt Routine Execution. To use a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set the interrupt priority ...
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R8C/1A Group, R8C/1B Group 10.4.3 Stop Mode Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU and peripheral functions that use these clocks stop operating. The least power required to ...
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R8C/1A Group, R8C/1B Group FMR0 Register Time until Flash Memory FMSTP Bit 0 Period of system clock × 12 cycles + 30 µs (max.) (flash memory operates) 1 Period of system clock (flash memory stops) T0 Oscillation time of Stop ...
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R8C/1A Group, R8C/1B Group 10.5 Oscillation Stop Detection Function The oscillation stop detection function detects the stop of the main clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by bits OCD1 to OCD0 in the ...
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R8C/1A Group, R8C/1B Group Table 10.6 Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, and Voltage Monitor 2 Interrupts Generated Interrupt Source Oscillation stop detection ( (a) or (b) ) Watchdog timer Voltage monitor 2 Set bits OCD1 to ...
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R8C/1A Group, R8C/1B Group 10.6 Notes on Clock Generation Circuit 10.6.1 Stop Mode When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the CM10 bit in the CM1 register to ...
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R8C/1A Group, R8C/1B Group 11. Protection The protection function protects important registers from being easily overwritten when a program runs out of control. Figure 11.1 shows the PRCR Register. The registers protected by the PRCR register are listed below. • ...
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R8C/1A Group, R8C/1B Group 12. Interrupts 12.1 Interrupt Overview 12.1.1 Types of Interrupts Figure 12.1 shows the types of Interrupts. Software (non-maskable interrupt) Interrupt Hardware NOTES : 1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts. ...
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R8C/1A Group, R8C/1B Group 12.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable. 12.1.2.1 Undefined Instruction Interrupt The undefined instruction interrupt is generated when the UND instruction is executed. 12.1.2.2 Overflow Interrupt ...
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R8C/1A Group, R8C/1B Group 12.1.3 Special Interrupts Special interrupts are non-maskable. 12.1.3.1 Watchdog Timer Interrupt The watchdog timer interrupt is generated by the watchdog timer. Reset the watchdog timer after the watchdog timer interrupt is generated. For details, refer to ...
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R8C/1A Group, R8C/1B Group 12.1.5 Interrupts and Interrupt Vectors There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address ...
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R8C/1A Group, R8C/1B Group 12.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 12.2 lists the Relocatable Vector Tables. Table 12.2 Relocatable Vector Tables Interrupt Source +0 ...
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R8C/1A Group, R8C/1B Group 12.1.6 Interrupt Control The following describes enabling and disabling the maskable interrupts and setting the priority for acknowledgement. The explanation does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and ...
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R8C/1A Group, R8C/1B Group INT0 Interrupt Control Register Symbol INT0IC Bit Symbol ILVL0 ILVL1 ILVL2 IR POL — (b5) — (b7-b6) NOTES : 1. Only 0 can be w ritten to ...
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R8C/1A Group, R8C/1B Group 12.1.6.1 I Flag The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts. 12.1.6.2 IR Bit The ...
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R8C/1A Group, R8C/1B Group 12.1.6.4 Interrupt Sequence An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine execution. When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt priority level ...
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R8C/1A Group, R8C/1B Group 12.1.6.5 Interrupt Response Time Figure 12.6 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in the interrupt routine. The interrupt ...
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R8C/1A Group, R8C/1B Group 12.1.6.7 Saving a Register In the interrupt sequence, the FLG register and PC are saved to the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order ...
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R8C/1A Group, R8C/1B Group 12.1.6.8 Returning from an Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved to the stack, are automatically restored. The program, ...
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R8C/1A Group, R8C/1B Group 12.1.6.10 Interrupt Priority Judgement Circuit The interrupt priority judgement circuit selects the highest priority interrupt, as shown in Figure 12.10. Priority level of each interrupt Compare 0 INT3 Timer Z Timer X INT0 Timer C INT1 ...
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R8C/1A Group, R8C/1B Group 12.2 INT Interrupt 12.2.1 INT0 Interrupt The INT0 interrupt is generated by an INT0 input. When using the INT0 interrupt, the INT0EN bit in the INTEN register is set to 1 (enable). The edge polarity is ...
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R8C/1A Group, R8C/1B Group 12.2.2 INT0 Input Filter The INT0 input contains a digital filter. The sampling clock is selected by bits INT0F1 to INT0F0 in the INT0F register. The INT0 level is sampled every sampling clock cycle and if ...
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R8C/1A Group, R8C/1B Group 12.2.3 INT1 Interrupt The INT1 interrupt is generated by an INT1 input. The edge polarity is selected by the R0EDG bit in the TXMR register. When the CNTRSEL bit in the UCON register is set to ...
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R8C/1A Group, R8C/1B Group 12.2.4 INT3 Interrupt The INT3 interrupt is generated by an INT3 input. Set the TCC07 bit in the TCC0 register to 0 (INT3). When the TCC06 bit in the TCC0 register is set ...
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R8C/1A Group, R8C/1B Group Timer C Control Register Symbol TCC1 Bit Symbol TCC10 TCC11 TCC12 TCC13 TCC14 TCC15 TCC16 TCC17 NOTES : 1. When the same value from the INT3 2. ...
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R8C/1A Group, R8C/1B Group 12.3 Key Input Interrupt A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can be used as a key-on wake-up function to exit ...
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R8C/1A Group, R8C/1B Group (1) Key Input Enable Register Symbol KIEN Bit Symbol KI0EN KI0PL KI1EN KI1PL KI2EN KI2PL KI3EN KI3PL NOTE : 1. The IR bit in the KUPIC register may ...
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R8C/1A Group, R8C/1B Group 12.4 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi register ( 1). This interrupt is used as a break ...
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R8C/1A Group, R8C/1B Group Address Match Interrupt Enable Register Symbol AIER Bit Symbol AIER0 AIER1 — (b7-b2) Address Match Interrupt Register i(i = 0,1) (b23) (b19) (b16) (b15 ...
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R8C/1A Group, R8C/1B Group 12.5 Notes on Interrupts 12.5.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h ...
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R8C/1A Group, R8C/1B Group 12.5.5 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt ...
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R8C/1A Group, R8C/1B Group 12.5.6 Changing Interrupt Control Register Contents (a) The contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. If interrupt requests may be generated, disable interrupts ...
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R8C/1A Group, R8C/1B Group 13. Watchdog Timer The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is recommended to improve the reliability of the system. The watchdog timer contains ...
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R8C/1A Group, R8C/1B Group Option Function Select Register Symbol OFS Bit Symbol WDTON — (b1) ROMCR ROMCP1 — (b6-b4) CSPROINI NOTES : 1. The OFS register is on ...
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R8C/1A Group, R8C/1B Group Watchdog Timer Reset Register b7 b0 Symbol WDTR When 00h is w ritten before w riting FFh, the w atchdog timer is reset. The default value of the w atchdog timer is 7FFFh w hen count ...
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R8C/1A Group, R8C/1B Group 13.1 Count Source Protection Mode Disabled The count source of the watchdog timer is the CPU clock when count source protection mode is disabled. Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode ...
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R8C/1A Group, R8C/1B Group 13.2 Count Source Protection Mode Enabled The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. If the CPU clock stops when a program is out ...
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R8C/1A Group, R8C/1B Group 14. Timers The MCU has two 8-bit timers with 8-bit prescalers, and a 16-bit timer. The two 8-bit timers with 8-bit prescalers are timer X and timer Z. These timers contain a reload register to store ...
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R8C/1A Group, R8C/1B Group 14.1 Timer X Timer 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated at the same address, ...
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R8C/1A Group, R8C/1B Group Timer X Mode Register Symbol TXMR Bit Symbol TXMOD0 TXMOD1 R0EDG TXS TXOCNT TXMOD2 TXEDG TXUND NOTES : 1. The IR bit in the INT1IC register may be ...
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R8C/1A Group, R8C/1B Group Prescaler X Register b7 b0 Symbol Timer mode Pulse output mode Event counter mode Pulse w idth measurement mode Pulse period measurement mode Timer X Register b7 b0 Symbol Counts underflow of prescaler X Timer Count ...
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R8C/1A Group, R8C/1B Group 14.1.1 Timer Mode In timer mode, the timer counts an internally generated count source (refer to Table 14.2 Timer Mode Specifications). Figure 14.4 shows the TXMR Register in Timer Mode. Table 14.2 Timer Mode Specifications Item ...
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R8C/1A Group, R8C/1B Group 14.1.2 Pulse Output Mode In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is output from the CNTR0 pin each time the timer underflows (refer to Table 14.3 ...
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R8C/1A Group, R8C/1B Group Timer X Mode Register Symbol TXMR Bit Symbol TXMOD0 TXMOD1 R0EDG TXS TXOCNT TXMOD2 TXEDG TXUND NOTES : 1. The IR bit in ...
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R8C/1A Group, R8C/1B Group 14.1.3 Event Counter Mode In event counter mode, external signal inputs to the INT1/CNTR0 pin are counted (refer to Table 14.4 Event Counter Mode Specifications). Figure 14.6 shows the TXMR Register in Event Counter Mode. Table ...
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R8C/1A Group, R8C/1B Group 14.1.4 Pulse Width Measurement Mode In pulse width measurement mode, the pulse width of an external signal input to the INT1/CNTR0 pin is measured (refer to Table 14.5 Pulse Width Measurement Mode Specifications). Figure 14.7 shows ...
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R8C/1A Group, R8C/1B Group Timer X Mode Register Symbol TXMR Bit Symbol TXMOD0 TXMOD1 R0EDG TXS TXOCNT TXMOD2 TXEDG TXUND NOTES : 1. The IR bit ...
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R8C/1A Group, R8C/1B Group n = high level: the contents of TX register, low level: the contents of PREX register FFFFh Count start n 0000h Set program 1 TXS bit in TXMR register 0 1 Measured pulse ...
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R8C/1A Group, R8C/1B Group 14.1.5 Pulse Period Measurement Mode In pulse period measurement mode, the pulse period of an external signal input to the INT1/CNTR0 pin is measured (refer to Table 14.6 Pulse Period Measurement Mode Specifications). Figure 14.9 shows ...
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R8C/1A Group, R8C/1B Group Timer X Mode Register Symbol TXMR Bit Symbol TXMOD0 TXMOD1 R0EDG TXS TXOCNT TXMOD2 (2) TXEDG (2) TXUND NOTES : 1. The IR bit ...
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R8C/1A Group, R8C/1B Group Underflow signal of prescaler X Set program TXS bit in TXMR 1 register 0 Starts counting 1 CNTR0i pin input 0 Contents of timer X 0Fh Contents of read-out buffer1 TXEDG bit in ...
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R8C/1A Group, R8C/1B Group 14.1.6 Notes on Timer X • Timer X stops counting after a reset. Set the values in the timer and prescaler before the count starts. • Even if the prescaler and timer are read out in ...
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R8C/1A Group, R8C/1B Group 14.2 Timer Z Timer 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated at the same address. ...
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R8C/1A Group, R8C/1B Group Timer Z Mode Register Symbol TZMR Bit Symbol — (b3-b0) TZMOD0 TZMOD1 TZWC TZS NOTE : 1. Refer to 14.2.5 Notes on Tim er ...
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R8C/1A Group, R8C/1B Group Prescaler Z Register b7 b0 Timer mode Programmable w aveform generation mode Programmable one-shot generation mode Programmable w ait one-shot generation mode Timer Z Secondary Register b7 b0 Timer mode Programmable w aveform generation mode Programmable ...
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R8C/1A Group, R8C/1B Group Timer Z Output Control Register Symbol TZOC Bit Symbol TZOS — (b1) TZOCNT — (b7-b3) NOTES : 1. This bit is set hen the ...
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R8C/1A Group, R8C/1B Group Timer Count Source Setting Register Symbol TCSS Bit Symbol TXCK0 TXCK1 — (b3-b2) TZCK0 TZCK1 — (b7-b6) NOTE : 1. Do not sw itch ...
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R8C/1A Group, R8C/1B Group 14.2.1 Timer Mode In timer mode, a count source which is internally generated or timer X underflow is counted (refer to Table 14.7 Timer Mode Specifications). The TZSC register is not used in timer mode. Figure ...
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R8C/1A Group, R8C/1B Group Timer Z Mode Register Symbol TZMR Bit Symbol — (b3-b0) TZMOD0 TZMOD1 TZWC TZS NOTES : 1. When the TZS bit is ...
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R8C/1A Group, R8C/1B Group 14.2.2 Programmable Waveform Generation Mode In programmable waveform generation mode, the signal output from the TZOUT pin is inverted each time the counter underflows, while the values in registers TZPR and TZSC are counted alternately (refer ...
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R8C/1A Group, R8C/1B Group Timer Z Mode Register Symbol TZMR Bit Symbol — (b3-b0) TZMOD0 TZMOD1 TZWC TZS NOTES : 1. When the TZS bit ...
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R8C/1A Group, R8C/1B Group 1 TZS bit in TZMR register 0 Count source Prescaler Z underflow signal Contents of timer bit in TZIC register 0 1 TZOPL bit in PUM register 0 “H” TZOUT pin output “L” ...
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R8C/1A Group, R8C/1B Group 14.2.3 Programmable One-shot Generation Mode In programmable one-shot generation mode, one-shot pulse is output from the TZOUT pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 14.9 Programmable ...
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R8C/1A Group, R8C/1B Group Timer Z Mode Register Symbol TZMR Bit Symbol — (b3-b0) TZMOD0 TZMOD1 TZWC TZS NOTES : 1. When the TZS bit ...
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R8C/1A Group, R8C/1B Group 1 TZS bit in TZMR register 0 1 TZOS bit in TZOC register 0 Count source Prescaler Z underflow signal 1 INT0 pin input 0 Contents of timer bit in TZIC register 0 ...
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R8C/1A Group, R8C/1B Group 14.2.4 Programmable Wait One-Shot Generation Mode In programmable wait one-shot generation mode, a one-shot pulse is output from the TZOUT pin by a program or an external trigger input (input to the INT0 pin) (refer to ...
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R8C/1A Group, R8C/1B Group Table 14.10 Programmable Wait One-Shot Generation Mode Specifications Item Count sources Count operations Wait time One-shot pulse output time Count start conditions Count stop conditions Interrupt request generation timing TZOUT pin function INT0 pin function Read ...
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R8C/1A Group, R8C/1B Group Timer Z Mode Register Symbol TZMR Bit Symbol — (b3-b0) TZMOD0 TZMOD1 TZWC TZS NOTES : 1. When the TZS bit ...
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R8C/1A Group, R8C/1B Group TZS bit in TZMR 1 register 0 TZOS bit in TZOC 1 register 0 Count source Prescaler Z underflow signal 1 INT0 pin input 0 Contents of timer bit in TZIC register 0 ...
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R8C/1A Group, R8C/1B Group 14.2.5 Notes on Timer Z • Timer Z stops counting after a reset. Set the values in the timer and prescaler before the count starts. • Even if the prescaler and timer are read out in ...
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R8C/1A Group, R8C/1B Group 14.3 Timer C Timer 16-bit timer. Figure 14.23 shows a Block Diagram of Timer C. Figure 14.24 shows a Block Diagram of CMP Waveform Generation Unit. Figure 14.25 shows a Block Diagram of ...
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R8C/1A Group, R8C/1B Group TCC14 TCC15 Compare 0 interrupt signal Compare 1 interrupt signal TCC16 TCC17 TCC17 to TCC16 “H” = 11b “L” = 10b Reverse = 01b TCC15 to TCC14 Reverse = 01b “L” = 10b “H” = 11b ...
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R8C/1A Group, R8C/1B Group Timer C Register (b15) (b8 Counts internal count source. 0000h can be read w hen the TCC00 bit is set to 0 (count stops). Count value can be read w hen the TCC00 ...
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R8C/1A Group, R8C/1B Group Timer C Control Register Symbol TCC0 Bit Symbol TCC00 TCC01 TCC02 TCC03 TCC04 — (b5) TCC06 TCC07 NOTES : 1. Change this bit w hen the ...
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R8C/1A Group, R8C/1B Group Timer C Control Register Symbol TCC1 Bit Symbol TCC10 TCC11 TCC12 TCC13 TCC14 TCC15 TCC16 TCC17 NOTES : 1. When the same value is sampled from the ...
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R8C/1A Group, R8C/1B Group Timer C Output Control Register Symbol TCOUT Bit Symbol TCOUT0 TCOUT1 TCOUT2 TCOUT3 TCOUT4 TCOUT5 TCOUT6 TCOUT7 NOTE : 1. Set the bits w hich are not used ...
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R8C/1A Group, R8C/1B Group 14.3.1 Input Capture Mode In input capture mode, the edge of the TCIN pin input signal or the fRING128 clock is used as a trigger to latch the timer value and generate an interrupt request. The ...
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R8C/1A Group, R8C/1B Group FFFFh Count starts 0000h Set program 1 TCC00 bit in TCC0 register 0 The delay caused by digital filter and one count source cycle delay (max.) Measured pulse 1 (TCIN pin input) 0 ...
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R8C/1A Group, R8C/1B Group 14.3.2 Output Compare Mode In output compare mode, an interrupt request is generated when the value of the TC register matches the value of the TM0 or TM1 register. Table 14.12 shows the Output Compare Mode ...
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R8C/1A Group, R8C/1B Group Value set in TM1 register Count starts Value set in TM0 register 0000h Set program 1 TCC00 bit in TCC0 register bit in CMP0IC register bit in ...
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R8C/1A Group, R8C/1B Group 14.3.3 Notes on Timer C Access registers TC, TM0, and TM1 in 16-bit units. The TC register can be read in 16-bit units. This prevents the timer value from being updated between when the low-order bytes ...
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R8C/1A Group, R8C/1B Group 15. Serial Interface The serial interface consists of two channels (UART0 and UART1). Each UARTi ( has an exclusive timer to generate the transfer clock and operates independently. Figure 15.1 shows a ...
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R8C/1A Group, R8C/1B Group 1SP RXDi SP PAR SP 2SP 0 2SP SP PAR SP 1SP Figure 15.2 UARTi Transmit/Receive Unit Rev.1.30 Dec 08, 2006 Page 153 of 315 REJ09B0252-0130 Clock synchronous type PRYE = 0 Clock PAR UART (7 ...
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R8C/1A Group, R8C/1B Group UARTi Transmit Buffer Register ( (b15) (b8 Bit Symbol — (b8-b0) — (b15-b9) NOTES : 1. When the transfer data length is 9 bits, w rite data to high ...
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R8C/1A Group, R8C/1B Group UARTi Transmit / Receive Mode Register ( Symbol U0MR U1MR Bit Symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE — (b7) NOTES : ...
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R8C/1A Group, R8C/1B Group UARTi Transmit / Receive Control Register Symbol U0C0 U1C0 Bit Symbol CLK0 CLK1 — (b2) TXEPT — (b4) NCH CKPOL UFORM ...
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R8C/1A Group, R8C/1B Group UARTi Transmit / Receive Control Register Symbol U0C1 U1C1 Bit Symbol — (b7-b4) NOTE : 1. The RI ...
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R8C/1A Group, R8C/1B Group 15.1 Clock Synchronous Serial I/O Mode In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers ...
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R8C/1A Group, R8C/1B Group Table 15.2 Registers Used and Settings in Clock Synchronous Serial I/O Mode Register Bit U0TB U0RB OER U0BRG U0MR SMD2 to SMD0 CKDIR U0C0 CLK1 to CLK0 ...
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R8C/1A Group, R8C/1B Group • Example of transmit timing (when internal clock is selected) Transfer clock TE bit in U0C1 1 register 0 Set data in U0TB register TI bit in U0C1 1 register 0 Transfer from U0TB register to ...
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R8C/1A Group, R8C/1B Group 15.1.1 Polarity Select Function Figure 15.8 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity. • When the CKPOL bit in the U0C0 register = 0 ...
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R8C/1A Group, R8C/1B Group 15.1.3 Continuous Receive Mode Continuous receive mode is selected by setting the U0RRM bit in the UCON register to 1 (enables continuous receive mode). In this mode, reading the U0RB register sets the TI bit in ...
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R8C/1A Group, R8C/1B Group 15.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format. Table 15.4 lists the UART Mode Specifications. Table 15.5 lists the ...
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R8C/1A Group, R8C/1B Group Table 15.5 Registers Used and Settings for UART Mode Register Bit UiTB UiRB OER,FER,PER,SUM UiBRG UiMR SMD2 to SMD0 CKDIR STPS PRY, PRYE UiC0 CLK0, CLK1 TXEPT ...
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R8C/1A Group, R8C/1B Group • Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit) TC Transfer clock TE bit in UiC1 1 register 0 Write data to UiTB register TI bit in UiC1 1 register ...
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R8C/1A Group, R8C/1B Group • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) UiBRG output UiC1 register 1 RE bit 0 RXDi Transfer clock Reception triggered when transfer clock is generated by ...
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R8C/1A Group, R8C/1B Group 15.2.2 Bit Rate In UART mode, the bit rate is the frequency divided by the UiBRG ( register. UART Mode • Internal clock selected UiBRG register setting value = • External clock ...
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R8C/1A Group, R8C/1B Group 15.3 Notes on Serial Interface • When reading data from the UiRB register either in the clock asynchronous serial I/O mode or in the clock synchronous serial I/O mode. Ensure the data is read in 16-bit ...
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R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface The clock synchronous serial interface is configured as follows. Clock synchronous serial interface Clock synchronous serial I/O with chip select (SSU bus Interface The clock synchronous serial interface ...
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R8C/1A Group, R8C/1B Group 16.2 Clock Synchronous Serial I/O with Chip Select (SSU) Clock synchronous serial I/O with chip select supports clock synchronous serial data communication. Table 16.2 shows a Clock Synchronous Serial I/O with Chip Select Specifications and Figure ...
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R8C/1A Group, R8C/1B Group SSCK SCS SSO SSI 16, 32, 64, 128, or 256 Figure 16.1 Block Diagram of Clock Synchronous Serial I/O with Chip Select Rev.1.30 Dec 08, 2006 Page 171 of 315 REJ09B0252-0130 Internal ...
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R8C/1A Group, R8C/1B Group (4) SS Control Register Symbol SSCRH Bit Symbol CKS0 CKS1 CKS2 — (b4-b3) MSS RSSTP — (b7) NOTES : 1. The set clock is used w hen ...
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R8C/1A Group, R8C/1B Group (4) SS Control Register Symbol SSCRL Bit Symbol — (b0) SRES — (b3-b2) SOLP SOL — (b6) — (b7) NOTES : 1. Registers SSCRH, SSCRL, SSMR, SSER, ...
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R8C/1A Group, R8C/1B Group (2) SS Mode Register Symbol SSMR Bit Symbol BC0 BC1 BC2 — (b3) — (b4) CPHS CPOS MLS NOTES : 1. Refer to 16.2.1.1 Association betw een ...
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R8C/1A Group, R8C/1B Group (1) SS Enable Register Symbol SSER Bit Symbol CEIE — (b2-b1 RIE TEIE TIE NOTE : 1. Refer to 16.2.8.1 Accessing Registers Associated w ith Clock ...
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R8C/1A Group, R8C/1B Group (7) SS Status Register Symbol SSSR Bit Symbol CE — (b1) ORER — (b4-b3) RDRF TEND TDRE NOTES : 1. Writing 1 to CE, ORER, RDRF, TEND, or ...
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R8C/1A Group, R8C/1B Group (5) SS Mode Register Symbol SSMR2 Bit Symbol SSUMS CSOS SOOS SCKOS CSS0 CSS1 SCKS BIDE NOTES : 1. Refer to 16.2.2.1 Relationship betw een Data I/O ...
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R8C/1A Group, R8C/1B Group (1) SS Transmit Data Register Symbol SSTDR Store the transmit data. The stored transmit data is transferred to the SSTRSR register and transmission is started w hen it ...
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R8C/1A Group, R8C/1B Group 16.2.1 Transfer Clock The transfer clock can be selected among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8, and f1/4) and an external clock. When using clock synchronous serial I/O with chip select, set the ...
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R8C/1A Group, R8C/1B Group • SSUMS = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd edge), and CPOS bit = 0 (“H” when clock stops) SSCK SSO, SSI • SSUMS = 1 (4-wire bus communication ...
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R8C/1A Group, R8C/1B Group 16.2.2 SS Shift Register (SSTRSR) The SSTRSR register is a shift register for transmitting and receiving serial data. When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in ...
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R8C/1A Group, R8C/1B Group 16.2.3 Interrupt Requests Clock synchronous serial I/O with chip select has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the clock ...