MC908GR16VFAE Freescale Semiconductor, MC908GR16VFAE Datasheet - Page 177

• Manufacturer Part Number: MC908GR16VFAE
• Description: IC MCU 16K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR16VFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 15
System Integration Module (SIM)
15.1 Introduction
This section describes the system integration module (SIM). Together with the central processor unit
(CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in
Figure
controller that coordinates CPU and exception timing.
The SIM is responsible for:
Table 15-1
Freescale Semiconductor
•
•
•
•
•
Bus clock generation and control for CPU and peripherals:
–
–
Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
Interrupt control:
–
–
–
CPU enable/disable timing
Modular architecture expandable to 128 interrupt sources
15-2.
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
PORRST
Stop/wait/reset/break entry and recovery
Internal clock control
Acknowledge timing
Arbitration control timing
Vector address generation
IRST
R/W
IDB
IAB
shows the internal signal names used in this section.
Table 15-1
is a summary of the SIM input/output (I/O) registers. The SIM is a system state
Signal from the power-on reset module to the SIM
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Internal reset signal
Read/write signal
Table 15-1. Signal Name Conventions
MC68HC908GR16 Data Sheet, Rev. 5.0
Description
177