MC908GR16VFAE Freescale Semiconductor, MC908GR16VFAE Datasheet - Page 221

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MC908GR16VFAE

Manufacturer Part Number
MC908GR16VFAE
Description
IC MCU 16K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheets

Specifications of MC908GR16VFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Chapter 18
Timer Interface Module (TIM)
18.1 Introduction
This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a
timing reference with input capture, output compare, and pulse-width-modulation functions.
is a block diagram of the TIM.
This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
Freescale Semiconductor
BUS CLOCK
INTERNAL
TSTOP
TRST
16-BIT COMPARATOR
16-BIT COMPARATOR
16-BIT COMPARATOR
16-BIT COUNTER
TMODH:TMODL
TCH0H:TCH0L
TCH1H:TCH1L
16-BIT LATCH
16-BIT LATCH
CHANNEL 0
CHANNEL 1
PRESCALER
Figure 18-1. TIM Block Diagram
MC68HC908GR16 Data Sheet, Rev. 5.0
ELS0B
ELS1B
MS0A
MS1A
PS2
ELS0A
ELS1A
PRESCALER SELECT
PS1
MS0B
CH0F
CH1F
PS0
CH0MAX
CH1MAX
CH0IE
CH1IE
TOV0
TOV1
TOIE
TOF
INTERRUPT
INTERRUPT
INTERRUPT
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
PORT
PORT
Figure 18-1
T[1,2]CH0
T[1,2]CH1
221

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