MC908GR16AVFAE Freescale Semiconductor, MC908GR16AVFAE Datasheet
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MC68HC908GR16A Data Sheet M68HC08 Microcontrollers MC68HC908GR16A Rev. 1.0 03/2006 freescale.com ...
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... Clock Generator Module (CGM) 1.0 2006 erroneous information. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2004, 2006. All rights reserved. Freescale Semiconductor Description — ...
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... Revision History 4 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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... Chapter 16 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Chapter 17 Timebase Module (TBM 211 Chapter 18 Timer Interface Module (TIM1 and TIM2 215 Chapter 19 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Chapter 20 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Chapter 21 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 263 Freescale Semiconductor MC68HC908GR16A Data Sheet, Rev. 1.0 5 ...
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... List of Chapters 6 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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... FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.6.4 FLASH Mass Erase Operation 2.6.5 FLASH Program/Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6.6 FLASH Block Protection 2.6.7 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.6.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.6.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Freescale Semiconductor Chapter 1 General Description and and DDA SSA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CGMXFC and VSSAD/V ...
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... Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.3.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8 Chapter 3 Analog-to-Digital Converter (ADC DDAD ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SSAD ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 REFH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 REFL ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Chapter 4 Clock Generator Module (CGM) MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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... COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.4 Power-On Reset 6.3.5 Internal Reset 6.3.6 Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.7 COPD (COP Disable 6.3.8 COPRS (COP Rate Select 6.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Freescale Semiconductor ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 DDA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SSA Chapter 5 Configuration Register (CONFIG) Chapter 6 MC68HC908GR16A Data Sheet, Rev. 1.0 9 ...
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... Keyboard Module During Break Interrupts 103 9.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.7.1 Keyboard Status and Control Register 103 9.7.2 Keyboard Interrupt Enable Register 104 10 Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI) MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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... Timer Interface Module (TIM1 and TIM2 109 10.12.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.12.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.13 Timebase Module (TBM 109 10.13.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.14 Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Freescale Semiconductor Chapter 10 Low-Power Modes MC68HC908GR16A Data Sheet, Rev. 1.0 11 ...
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... Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.2.3 Internal Reset 131 13.2.3.1 Power-On Reset (POR 131 13.2.3.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12 Chapter 11 Low-Voltage Inhibit (LVI) Chapter 12 Input/Output (I/O) Ports Chapter 13 Resets and Interrupts MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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... Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14.4.3.2 Character Reception 151 14.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Freescale Semiconductor Chapter 14 MC68HC908GR16A Data Sheet, Rev. 1.0 13 ...
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... SIM Counter During Stop Mode Recovery 179 15.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15.5 Exception Control 179 15.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.5.1.3 Interrupt Status Registers 183 14 Chapter 15 System Integration Module (SIM) MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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... MOSI (Master Out/Slave In 205 16.11.3 SPSCK (Serial Clock 205 16.11.4 SS (Slave Select 206 16.12 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.12.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.12.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 16.12.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Freescale Semiconductor Chapter 16 MC68HC908GR16A Data Sheet, Rev. 1.0 15 ...
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... TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 18.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 18.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 18.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 18.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 16 Chapter 17 Timebase Module (TBM) Chapter 18 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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... ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 20.11 3.3-Volt ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 20.12 5.0-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 20.13 3.3-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 20.14 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 20.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Freescale Semiconductor Chapter 19 Development Support Chapter 20 Electrical Specifications MC68HC908GR16A Data Sheet, Rev. 1.0 ...
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... Table of Contents Ordering Information and Mechanical Specifications 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 21.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 18 Chapter 21 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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... Kbytes of on-chip FLASH memory • 1 Kbyte of on-chip random-access memory (RAM) • 406 bytes of FLASH programming routines read-only memory (ROM security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor (1) MC68HC908GR16A Data Sheet, Rev. 1.0 19 ...
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... Port bits: PTB0–PTB7; 8-channel ADC module – Port C is only 7 bits: PTC0–PTC6 – Port bits: PTD0–PTD7; shared with SPI, TIM1, and TIM2 modules – Port E is only 6 bits: PTE0–PTE5; shared with ESCI module 20 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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... MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908GR16A. 1.4 Pin Assignments Figure 1-2 and Figure 1-3 illustrate the pin assignments for the 32-pin LQFP and 48-pin LQFP respectively. Freescale Semiconductor MC68HC908GR16A Data Sheet, Rev. 1.0 MCU Block Diagram 21 ...
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... PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1 (1), (2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
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... PTE0/TxD PTE1/RxD PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK Figure 1-2. 32-Pin LQFP Pin Assignments RST 1 PTE0/TxD PTE1/RxD PTE2 PTE3 PTE4 PTE5 IRQ PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK 12 Figure 1-3. 48-Pin LQFP Pin Assignments Freescale Semiconductor RST IRQ MC68HC908GR16A Data Sheet, Rev. 1.0 Pin Assignments ...
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... Chapter 15 System Integration Module (SIM). 1.5.4 External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See Chapter 8 External Interrupt (IRQ). 24 and MCU 0.1 µ Figure 1-4. Power Supply Bypassing MC68HC908GR16A Data Sheet, Rev. 1.0 Figure 1 Chapter 4 Freescale Semiconductor ...
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... Chapter 18 Timer Interface Module (TIM1 and Module, and Chapter 12 Input/Output (I/O) These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis. Freescale Semiconductor and V ) DDA SSA ...
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... Chapter 12 Input/Output (I/O) Ports. Any unused inputs and I/O ports should be tied to an appropriate logic level (either not require termination, termination is recommended to reduce the possibility of static damage. 26 NOTE ). Although the I/O ports of the MC68HC908GR16A do SS MC68HC908GR16A Data Sheet, Rev. 1.0 and Freescale Semiconductor ...
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... BRKSCR • $FE0C; LVI status register, LVISR • $FF7E; FLASH block protect register, FLBPR Data registers are shown in Figure Freescale Semiconductor 2-2. Table 2 list of vector locations. MC68HC908GR16A Data Sheet, Rev. 1.0 Figure 2-1, includes: 27 ...
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... FLASH CONTROL REGISTER (FLCR) BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) LVI STATUS REGISTER (LVISR) UNIMPLEMENTED 3 BYTES UNIMPLEMENTED 16 BYTES FOR A-FAMILY PART MONITOR ROM 350 BYTES FLASH BLOCK PROTECT REGISTER (FLBPR) UNIMPLEMENTED 93 BYTES FLASH VECTORS 36 BYTES Freescale Semiconductor ...
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... Register (SCIACTL) Write: See page 170. Reset: Read: ESCI Arbiter Data $000B Register (SCIADAT) Write: See page 171. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset PTB7 PTB6 PTB5 PTB4 ...
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... SCTE TC SCRF IDLE Unimplemented R = Reserved MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 DDRE3 DDRE2 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 CPHA SPWOM SPE SPTIE SPTE MODFEN SPR1 SPR0 WAKE ILTY PEN PTY RWU SBK ORIE NEIE FEIE PEIE BKF RPF Unaffected Freescale Semiconductor ...
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... Reset: Read: Timer 1 Counter $0022 Register Low (T1CNTL) Write: See page 226. Reset: Read: Timer 1 Counter Modulo $0023 Register High (T1MODH) Write: See page 227. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit Unaffected by reset LINT LINR ...
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... Indeterminate after reset TOF 0 TOIE TSTOP 0 TRST Bit Bit Bit Bit Unimplemented R = Reserved MC68HC908GR16A Data Sheet, Rev. 1 Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit Bit 0 0 PS2 PS1 PS0 Bit Bit Bit Bit Unaffected Freescale Semiconductor ...
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... Register (PMSL) Write: See page 70. Reset: Read: PLL VCO Select Range $003A Register (PMRS) Write: See page 70. Reset: Read: $003B Reserved Write: Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit CH0F CH0IE MS0B MS0A Bit Indeterminate after reset ...
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... IF13 IF12 IF11 IF20 IF19 Unimplemented R = Reserved MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 ADCH3 ADCH2 ADCH1 ADCH0 AD9 AD8 A3 AD2 AD1 AD0 0 MODE1 MODE0 SBSW (Note ILAD MODRST LVI IF2 IF1 IF10 IF9 IF8 IF7 IF18 IF17 IF16 IF15 Unaffected Freescale Semiconductor ...
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... Write: See page 113. Reset: Read: FLASH Block Protect (1) $FF7E Register (FLBPR) Write: See page 43. Reset: 1. Non-volatile FLASH register Read: COP Control Register $FFFF (COPCTL) Write: See page 81. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit Bit ...
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... PLL Vector (High) IF2 $FFF9 PLL Vector (Low) $FFFA IRQ Vector (High) IF1 $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) MC68HC908GR16A Data Sheet, Rev. 1.0 Vector Freescale Semiconductor ...
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... FLASH block protect register • $FFDC–$FFFF; these locations are reserved for user-defined interrupt and reset vectors A security feature prevents viewing of the FLASH contents. Freescale Semiconductor NOTE NOTE NOTE NOTE MC68HC908GR16A Data Sheet, Rev. 1.0 Random-Access Memory (RAM) ...
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... Program operation selected 0 = Program operation unselected 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users HVEN MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 MASS ERASE PGM Freescale Semiconductor ...
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... Clear the HVEN bit. (typical 1 µs), the memory can be accessed in read mode again. 10. After a time, t RCV 1. When in monitor mode, with security sequence failed (see of any FLASH address. Freescale Semiconductor NOTE (1) within the FLASH memory address range. NOTE 19.3.2 Security), write to the FLASH block protect register instead MC68HC908GR16A Data Sheet, Rev ...
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... Care must be taken within the FLASH array memory space such as the COP control register (COPCTL) at $FFFF highly recommended that interrupts be disabled during program/ erase operations. 40 NOTE NOTE NOTE NOTE NOTE MC68HC908GR16A Data Sheet, Rev. 1.0 (Figure 2 flowchart Freescale Semiconductor ...
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... IRQ pin will bypass the block protection so that all of the memory included in the block protect register is open for program and erase operations. The FLASH block protect register is not protected with special hardware or software. Therefore, if this page is not protected by FLBPR the register is erased by either a page or mass erase operation. Freescale Semiconductor NOTE maximum or t maximum. t PROG ...
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... WAIT FOR A TIME, t PGS 7 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED 8 WAIT FOR A TIME, t PROG COMPLETED PROGRAMMING THIS ROW MC68HC908GR16A Data Sheet, Rev. 1.0 Y CLEAR PGM BIT WAIT FOR A TIME, t NVH CLEAR HVEN BIT WAIT FOR A TIME, t RCV END OF PROGRAMMING Freescale Semiconductor ...
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... Figure 2-6. FLASH Block Protect Start Address Table 2-2. Examples of Protect Address Ranges BPR[7:0] $00 $01 (0000 0001) $02 (0000 0010) $03 (0000 0011) $04 (0000 0100) $FC (1111 1100) $FD (1111 1101) $FE (1111 1110) $FF Freescale Semiconductor BPR6 BPR5 BPR4 BPR3 Unaffected by reset. Initial value from factory is 1. 16-BIT MEMORY ADDRESS 1 ...
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... FLASH, otherwise the operation will discontinue, and the FLASH will be on standby mode Standby mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH minimum. 44 NOTE MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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... I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. A read of a port pin in use by the ADC will return a 0. Freescale Semiconductor 3-2. MC68HC908GR16A Data Sheet, Rev. 1.0 ...
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... PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1 (1), (2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
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... The ADC input voltage must always be greater than Connect the V DDAD pin, and connect the V The V pin should be routed carefully for maximum noise immunity. DDAD Freescale Semiconductor DDRBx PTBx DISABLE ADC DATA REGISTER ADC VOLTAGE IN (V ADIN ADC ...
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... Finally, 8-bit truncation mode will place the eight MSBs in the ADC data register low, ADRL. The two LSBs are dropped. This mode of operation ADC cycles ADC frequency MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
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... A CPU interrupt is generated if the COCO bit The COCO bit is not used as a conversion complete flag when interrupts are enabled. 3.6 Low-Power Modes The WAIT and STOP instruction can put the MCU in low power-consumption standby modes. Freescale Semiconductor NOTE Figure 3-3. ...
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... External filtering is often necessary to ensure a clean V DD NOTE carefully and place bypass REFH may improve common mode noise rejection. MC68HC908GR16A Data Sheet, Rev. 1.0 pin to the same voltage DDAD for good results. DDAD pin to the same voltage SSAD REFH REFH close and REFH Freescale Semiconductor for ...
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... Conversion completed (AIEN = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1) The write function of the COCO bit is reserved. When writing to the ADSCR register, always have the COCO bit position. Freescale Semiconductor ) REFL as its lower voltage reference pin. By default, connect the V REFL ...
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... Table 3-1. NOTE Table 3-1. Mux Channel Select ADCH2 ADCH1 ADCH0 ↓ ↓ ↓ MC68HC908GR16A Data Sheet, Rev. 1.0 Table 3-1. Care should (1) Input Select PTB0/AD0 PTB1/AD1 PTB2/AD2 PTB3/AD3 PTB4/AD4 PTB5/AD5 PTB6/AD6 PTB7/AD7 Unused V REFH V REFL ADC power off Freescale Semiconductor ...
Page 53
... All subsequent results will be lost until the ADRH and ADRL reads are completed. Address: $003D Bit 7 Read: 0 Write: Reset: Address: $003E Read: AD7 Write: Reset: Figure 3-6. ADC Data Register High (ADRH) and Low (ADRL) Freescale Semiconductor AD8 AD7 AD6 AD5 Unaffected by reset AD0 Unaffected by reset ...
Page 54
... AD8 AD7 AD6 AD5 Unaffected by reset AD0 Unaffected by reset = Unimplemented Unaffected by reset AD8 AD7 AD6 AD5 Unaffected by reset = Unimplemented MC68HC908GR16A Data Sheet, Rev. 1.0 ADRH 2 1 Bit 0 AD4 AD3 AD2 ADRL ADRH 2 1 Bit ADRL AD4 AD3 AD2 Freescale Semiconductor ...
Page 55
... MODE1 and MODE0 select among four modes of operation. The manner in which the ADC conversion results will be placed in the ADC data registers is controlled by these modes of operation. Reset returns right-justified mode 8-bit truncation mode 01 = Right justified mode 10 = Left justified mode 11 = Left justified signed data mode Freescale Semiconductor ADIV1 ADIV0 ...
Page 56
... Analog-to-Digital Converter (ADC) 56 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 57
... Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 4-1 shows the structure of the CGM. Freescale Semiconductor MC68HC908GR16A Data Sheet, Rev. 1.0 57 ...
Page 58
... AUTOMATIC INTERRUPT MODE CONTROL CONTROL AUTO ACQ PLLIE PLLF Figure 4-1. CGM Block Diagram MC68HC908GR16A Data Sheet, Rev. 1.0 CGMXCLK (TO: SIM, TIMEBASE, ADC) A CLOCK ÷ 2 SELECT CIRCUIT * WHEN CGMOUT = B CGMVCLK Freescale Semiconductor CGMOUT (TO SIM) PTB4 MONITOR MODE USER MODE CGMINT (TO SIM) ...
Page 59
... CGMRCLK. Therefore, the speed of the lock detector is directly proportional to the reference frequency The circuit determines the mode of the PLL and the lock condition based on this RCLK comparison. Freescale Semiconductor VRS , (71.4 kHz) times a linear factor, L, and a power-of-two factor PLL. Modes. The value of the external capacitor and the MC68HC908GR16A Data Sheet, Rev ...
Page 60
... PLL Bandwidth Control 4.3.8 Base Clock Selector Circuit.) The PLL is automatically in Register read-only indicator of the mode of Modes.) 4.8 Acquisition/Lock Time Specifications 4.8 Acquisition/Lock Time Specifications Register.) MC68HC908GR16A Data Sheet, Rev. 1.0 Register.) 4.5.2 PLL 4.3.8 Base Clock Selector for for Freescale Semiconductor ...
Page 61
... CGMXCLK), cost requirements, or ideally, as high as the specified range allows. See Specifications. After choosing N, the actual bus frequency can be determined using equation in 2 above. Freescale Semiconductor , after entering tracking mode before selecting the PLL as the AL Table 4-1. Variable Definitions ...
Page 62
... NOM f VCLK L = Round NOM VRS NOM E × NOM ≤ -------------------------- - f – f VRS VCLK VCLK VRS VCLKDES NOTE MC68HC908GR16A Data Sheet, Rev. 1.0 and f . VCLK BUS Table 4- (1) 2 VRS and f . For proper operation, VCLKDES , and f must be as close as possible VRS Freescale Semiconductor . The ...
Page 63
... VCO clock. The VCO clock also cannot be selected as the base clock source if the factor L is programmed This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock. Freescale Semiconductor Table 4-3. Numeric Example PCTL f ...
Page 64
... Note: Filter network in box can be replaced with a single capacitor, but will degrade stability. 64 CGMXCLK CGMXFC OSC2 Component Filter C 2 Figure 4-2. CGM External Connections MC68HC908GR16A Data Sheet, Rev. 1.0 Figure V V SSA DDA V DD CBYP C F2 0.1 µF Freescale Semiconductor 4-2. ...
Page 65
... Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (f directly from the crystal oscillator circuit. and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may Freescale Semiconductor 4-2.) NOTE ) ...
Page 66
... AUTO ACQ MUL7 MUL6 MUL5 VRS7 VRS6 VRS5 Unimplemented Figure 4-3. CGM I/O Register Summary MC68HC908GR16A Data Sheet, Rev. 1 BCS R R VPR1 MUL11 MUL10 MUL9 MUL4 MUL3 MUL2 MUL1 VRS4 VRS3 VRS2 VRS1 Reserved Freescale Semiconductor Bit 0 VPR0 MUL8 0 MUL0 0 VRS0 ...
Page 67
... CGMXCLK divided by two drives CGMOUT PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and Freescale Semiconductor ...
Page 68
... Circuit.). VRS 4.3.3 PLL Circuits, Register.) VCO Power-of-Two ( NOTE 4.3.6 Programming the PLL LOCK 0 0 ACQ Reserved MC68HC908GR16A Data Sheet, Rev. 1.0 . VPR1:VPR0 cannot be written when the 4.3.6 Programming the Range Multiplier for detailed instructions 2 1 Bit Freescale Semiconductor PLL, and ...
Page 69
... Reset initializes the registers to $0040 for a default multiply value of 64. The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). PMSH[7:4] — Unimplemented Bits These bits have no function and always read as 0s. Freescale Semiconductor ...
Page 70
... PLL Circuits and 4.3.6 Programming the NOTE VRS6 VRS5 VRS4 VRS3 NOTE for detailed instructions on selecting the proper value MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 MUL2 MUL1 MUL0 PLL.) MUL7–MUL0 cannot 2 1 Bit 0 VRS2 VRS1 VRS0 4.3.6 Freescale Semiconductor ...
Page 71
... Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. Freescale Semiconductor PLL, and 4.5.1 PLL Control . VRS7– ...
Page 72
... Acquisition and lock times are designed short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. 72 19.2.2.4 SIM Break Flag Control MC68HC908GR16A Data Sheet, Rev. 1.0 Register. Freescale Semiconductor ...
Page 73
... In general, a slightly larger capacitor provides more stability at the expense of increased lock time. CGMXFC SSA (A) Freescale Semiconductor PLL.) 4.8.3 Choosing a . The power supply potential alters the DDA Time, the external filter network is critical to the Figure 4-9 (A). Refer to ...
Page 74
... Clock Generator Module (CGM) Table 4-5. Example Filter Component Values f RCLK 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 8.2 nF 820 pF 4.7 nF 470 pF 3.3 nF 330 pF 2.2 nF 220 pF 1.8 nF 180 pF 1.5 nF 150 pF 1.2 nF 120 100 pF MC68HC908GR16A Data Sheet, Rev 2.2 nF Freescale Semiconductor ...
Page 75
... FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Address: $001E Bit 7 6 Read Write: Reset Unimplemented Figure 5-1. Configuration Register 2 (CONFIG2) Freescale Semiconductor NOTE Figure 5-1 and TBMCLKSEL OSCENINSTOP ESCIBDSRC Reserved MC68HC908GR16A Data Sheet, Rev ...
Page 76
... Chapter 4 Clock Generator Module (CGM) (CGM). This function is used to keep the timebase running while Chapter 17 Timebase Module Module. MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 SSREC STOP COPD (TBM). When clear, oscillator will cease Chapter 14 Enhanced Serial Chapter 6 Computer Operating Chapter 11 Low-Voltage Inhibit Freescale Semiconductor for (LVI). ...
Page 77
... STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. See 1 = COP module disabled 0 = COP module enabled Freescale Semiconductor Chapter 11 Low-Voltage Inhibit NOTE NOTE Chapter 6 Computer Operating Properly (COP) MC68HC908GR16A Data Sheet, Rev. 1.0 Functional Description (LVI) ...
Page 78
... Configuration Register (CONFIG) 78 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 79
... COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) 1. See Chapter 15 System Integration Module (SIM) Freescale Semiconductor SIM MODULE 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER for more details. ...
Page 80
... The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up. 6.3.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. 80 NOTE NOTE Figure 6-1. MC68HC908GR16A Data Sheet, Rev. 1.0 . During the break state, TST 6.4 COP Freescale Semiconductor ...
Page 81
... TST 6.7 Low-Power Modes The WAIT and STOP instructions put the microcontroller unit (MCU) in low power-consumption standby modes. 6.7.1 Wait Mode The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout. Freescale Semiconductor Low byte of reset vector ...
Page 82
... STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset. 6.8 COP Module During Break Mode The COP is disabled during a break interrupt when present on the RST pin. TST MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 83
... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor MC68HC908GR16A Data Sheet, Rev. 1.0 83 ...
Page 84
... CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H:X) MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 Bit Freescale Semiconductor ...
Page 85
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: Freescale Semiconductor ...
Page 86
... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result NOTE MC68HC908GR16A Data Sheet, Rev. 1 Bit Freescale Semiconductor ...
Page 87
... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Freescale Semiconductor MC68HC908GR16A Data Sheet, Rev. 1.0 Arithmetic/Logic Unit (ALU) ...
Page 88
... REL 27 rr – – – – – – REL – – – – – – REL 28 rr – – – – – – REL 29 rr – – – – – – REL 22 rr Freescale Semiconductor ...
Page 89
... Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? IRQ = 1 PC ← (PC rel ? IRQ = 0 (A) & (M) ⊕ PC ← (PC rel ? ( – – – – – – REL PC ← ...
Page 90
... INH 4A INH 5A – – – IX1 SP1 9E6A ff – – – – INH 52 IMM A8 ii DIR B8 dd EXT IX2 – – – IX1 SP1 9EE8 ff SP2 9ED8 ee ff DIR 3C dd INH 4C INH 5C – – – IX1 SP1 9E6C ff Freescale Semiconductor ...
Page 91
... ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack Freescale Semiconductor Description PC ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← Unconditional Address A ← (M) H:X ← (M ← (M) ...
Page 92
... DIR 35 dd – – 0 – – – INH 8E DIR BF dd EXT IX2 – – – IX1 SP1 9EEF ff SP2 9EDF ee ff IMM A0 ii DIR B0 dd EXT IX2 – – IX1 SP1 9EE0 ff SP2 9ED0 ee ff Freescale Semiconductor ...
Page 93
... M Memory location N Negative bit 7.8 Opcode Map See Table 7-2. Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...
Page 94
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 95
... The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When an interrupt pin is edge-triggered only (MODE = 0), the interrupt remains set until a vector fetch, software clear, or reset occurs. Freescale Semiconductor MC68HC908GR16A Data Sheet, Rev. 1.0 95 ...
Page 96
... Figure 8-1. IRQ Module Block Diagram NOTE Bit Unimplemented Figure 8-2. IRQ I/O Register Summary MC68HC908GR16A Data Sheet, Rev. 1.0 TO CPU FOR BIL/BIH INSTRUCTIONS IRQF IRQ SYNCHRONIZER INTERRUPT REQUEST TO MODE HIGH SELECT VOLTAGE LOGIC DETECT IRQF 0 IMASK ACK Freescale Semiconductor Bit 0 MODE 0 ...
Page 97
... To protect CPU interrupt flags during the break state, write the BCFE bit. With BCFE at 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ interrupt flags. Freescale Semiconductor NOTE Support. ...
Page 98
... MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only IRQF MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 0 IMASK MODE ACK Freescale Semiconductor ...
Page 99
... If the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled. Freescale Semiconductor MC68HC908GR16A Data Sheet, Rev. 1.0 99 ...
Page 100
... PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1 (1), (2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
Page 101
... If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFE0 and $FFE1. • Return of all enabled keyboard interrupt pins to a high level — As long as any enabled keyboard interrupt pin is low, the keyboard interrupt remains set. Freescale Semiconductor ACKK V DD CLR ...
Page 102
... The WAIT and STOP instructions put the microcontroller unit (MCU) in low power-consumption standby modes. 9.5.1 Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 102 NOTE MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 103
... This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit Keyboard interrupt pending keyboard interrupt pending ACKK — Keyboard Acknowledge Bit Writing this write-only bit clears the keyboard interrupt request. ACKK always reads as 0. Reset clears ACKK. Freescale Semiconductor 9.7.1 Keyboard Status and Control ...
Page 104
... Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register PTAx pin enabled as keyboard interrupt pin 0 = PTAx pin not enabled as keyboard interrupt pin 104 KBIE6 KBIE5 KBIE4 KBIE3 MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...
Page 105
... The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry. Freescale Semiconductor MC68HC908GR16A Data Sheet, Rev. 1.0 Chapter 5 ...
Page 106
... CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If the OSCENINSTOP bit in the CONFIG2 register is set, then the phase locked loop is shut off, but the oscillator will continue to operate in stop mode. 106 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 107
... Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. Freescale Semiconductor Computer Operating Properly Module (COP) MC68HC908GR16A Data Sheet, Rev. 1.0 ...
Page 108
... The SPI module is inactive in stop mode. The STOP instruction does not affect SPI register states. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset. 108 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 109
... Low-voltage inhibit (LVI) reset — A power supply voltage below the V and loads the program counter with the contents of locations $FFFE and $FFFF. Freescale Semiconductor MC68HC908GR16A Data Sheet, Rev. 1.0 Timer Interface Module (TIM1 and TIM2) voltage resets the MCU ...
Page 110
... The short stop recovery bit, SSREC, in the CONFIG1 register controls the oscillator stabilization delay during stop recovery. Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles. Use the full stop recovery time (SSREC = 0) in applications that use an external crystal. 110 NOTE MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 111
... V TRIPR V which will re-trigger the power-on reset and reset the trip point to 3-V operation. Freescale Semiconductor voltage falls below the LVI trip falling voltage voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI falls below a voltage, V ...
Page 112
... LVI resets allows the LVI TRIPF falls below the V level. In the configuration register, the DD TRIPF MC68HC908GR16A Data Sheet, Rev. 1.0 , which causes the MCU TRIPR LVISTOP FROM CONFIG1 LVI RESET level, software can monitor V DD Freescale Semiconductor Bit polling ...
Page 113
... V 11.5 LVI Interrupts The LVI module does not generate interrupt requests. 11.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. Freescale Semiconductor fall below V ), the LVI will maintain a reset condition until DD TRIPF . This prevents a condition in which the MCU is ...
Page 114
... Stop Mode If enabled in stop mode (LVISTOP bit in the configuration register is set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. 114 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 115
... See page 122. Reset: Read: Port D Data Register $0003 (PTD) Write: See page 124. Reset: Read: Data Direction Register A $0004 (DDRA) Write: See page 118. Reset: Freescale Semiconductor NOTE Bit PTA7 PTA6 PTA5 PTB7 PTB6 PTB5 1 PTC6 PTC5 PTD7 PTD6 PTD5 ...
Page 116
... PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0 Unimplemented MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE3 PTE2 PTE1 PTE0 DDRE3 DDRE2 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Freescale Semiconductor ...
Page 117
... Freescale Semiconductor DDR Module Control DDRA0 KBIE0 DDRA1 KBIE1 DDRA2 KBIE2 DDRA3 KBIE3 KBD DDRA4 KBIE4 DDRA5 KBIE5 DDRA6 KBIE6 DDRA7 KBIE7 DDRB0 DDRB1 DDRB2 DDRB3 ADC ADCH4–ADCH0 DDRB4 DDRB5 DDRB6 DDRB7 DDRC0 DDRC1 DDRC2 DDRC3 DDRC4 DDRC5 DDRC6 DDRD0 ...
Page 118
... PTA3 Unaffected by reset KBD6 KBD5 KBD4 KBD3 Figure 12-2. Port A Data Register (PTA) Chapter 9 Keyboard Interrupt Module (KBI DDRA6 DDRA5 DDRA4 DDRA3 NOTE MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 PTA2 PTA1 PTA0 KBD2 KBD1 KBD0 2 1 Bit 0 DDRA2 DDRA1 DDRA0 Freescale Semiconductor ...
Page 119
... Don’t care 2. I/O pin pulled internal pullup device DD 3. Writing affects data register, but does not affect input. 4. Hi-Z = High impedance Freescale Semiconductor PTAPUEx DDRAx RESET PTAx Figure 12-4. Port A I/O Circuit Table 12-2 summarizes the operation of the port A pins. ...
Page 120
... I/O ports. 120 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTB6 PTB5 PTB4 PTB3 Unaffected by reset AD6 AD5 AD4 AD3 Figure 12-6. Port B Data Register (PTB) NOTE MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 PTAPUE2 PTAPUE1 PTAPUE0 Bit 0 PTB2 PTB1 PTB0 AD2 AD1 AD0 Freescale Semiconductor ...
Page 121
... DDRB PTB I/O Pin Bit Bit Mode ( Input, Hi Output Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. Freescale Semiconductor DDRB6 DDRB5 DDRB4 DDRB3 NOTE DDRBx RESET PTBx Figure 12-8 ...
Page 122
... Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 122 PTC6 PTC5 PTC4 PTC3 Unaffected by reset Figure 12-9. Port C Data Register (PTC DDRC6 DDRC5 DDRC4 DDRC3 NOTE MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 PTC2 PTC1 PTC0 2 1 Bit 0 DDRC2 DDRC1 DDRC0 Freescale Semiconductor ...
Page 123
... Don’t care 2. I/O pin pulled internal pullup device Writing affects data register, but does not affect input. 4. Hi-Z = High impedance Freescale Semiconductor DDRCx RESET PTCx Figure 12-11. Port C I/O Circuit Table 12-4 summarizes the operation of the port C pins. Table 12-4. Port C Pin Functions ...
Page 124
... I/O pins or general-purpose I/O pins. See 124 PTCPUE5 PTCPUE4 PTCPUE3 PTD6 PTD5 PTD4 PTD3 Unaffected by reset T2CH0 T1CH1 T1CH0 SPSCK Chapter 18 Timer Interface Module (TIM1 and MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 PTCPUE2 PTCPUE1 PTCPUE0 Bit 0 PTD2 PTD1 PTD0 MOSI MISO SS TIM2). Freescale Semiconductor ...
Page 125
... These read/write bits control port D data direction. Reset clears DDRD7–DDRD0, configuring all port D pins as inputs Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from Freescale Semiconductor Chapter 18 Timer Interface Module (TIM1 and Table 12- ...
Page 126
... I/O Pin Mode Read/Write (2) Input, V DDRD7–DDRD0 DD (4) DDRD7–DDRD0 Input, Hi-Z Output DDRD7–DDRD0 MC68HC908GR16A Data Sheet, Rev. 1 PTDPUEx INTERNAL PULLUP DEVICE PTDx Accesses to PTD Read Write Pin PTD7–PTD0 Pin PTD7–PTD0 PTD7–PTD0 PTD7–PTD0 Freescale Semiconductor (3) (3) ...
Page 127
... E. Reset has no effect on port E data. Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the ESCI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See Freescale Semiconductor ...
Page 128
... E I/O logic. READ DDRE ($000C) WRITE DDRE ($000C) WRITE PTE ($0008) READ PTE ($0008) 128 DDRE5 DDRE4 DDRE3 NOTE DDREx RESET PTEx Figure 12-19. Port E I/O Circuit MC68HC908GR16A Data Sheet, Rev. 1.0 Module. Module Bit 0 DDRE2 DDRE1 DDRE0 PTEx Freescale Semiconductor ...
Page 129
... X Input, Hi Output Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. Freescale Semiconductor Table 12-6 summarizes the operation of the port E pins. Table 12-6. Port E Pin Functions Accesses to DDRE Read/Write (2) DDRE5–DDRE0 DDRE5–DDRE0 MC68HC908GR16A Data Sheet, Rev. 1.0 ...
Page 130
... Input/Output (I/O) Ports 130 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 131
... A power-on reset (POR internal reset caused by a positive transition on the V POR must go below V to reset the MCU. This distinguishes between a reset and a POR. The POR is POR not a brown-out detector, low-voltage detector, or glitch detector. Freescale Semiconductor , generates an external reset. An external reset sets the PIN bit RL MC68HC908GR16A Data Sheet, Rev. 1.0 pin. V ...
Page 132
... An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. An illegal opcode reset sets the ILOP bit in the SIM reset status register. 132 4096 32 CYCLES CYCLES Figure 13-1. Power-On Reset Recovery is below the V DD MC68HC908GR16A Data Sheet, Rev. 1.0 voltage TRIPR voltage and during the oscillator TRIPR Freescale Semiconductor ...
Page 133
... Last reset caused by an illegal opcode 0 = POR or read of SRSR since any reset ILAD — Illegal Address Reset Bit 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR since any reset Freescale Semiconductor at that time, then the PIN bit in the SRSR may be set IH NOTE 6 ...
Page 134
... CONDITION CODE REGISTER 1 ACCUMULATOR 2 (1) INDEX REGISTER (LOW BYTE) 3 PROGRAM COUNTER (HIGH BYTE) 4 PROGRAM COUNTER (LOW BYTE) 5 • • • $00FF DEFAULT ADDRESS ON RESET Figure 13-3. Interrupt Stacking Order MC68HC908GR16A Data Sheet, Rev. 1.0 UNSTACKING ORDER Freescale Semiconductor ...
Page 135
... The software interrupt (SWI) instruction causes a non-maskable interrupt. A software interrupt pushes PC onto the stack. An SWI does not push PC – hardware interrupt does. 13.3.2.2 Break Interrupt The break module causes the CPU to execute an SWI instruction at a software-programmable break point. Freescale Semiconductor CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE ...
Page 136
... INSTRUCTION INSTRUCTION 136 YES BREAK ? NO NO YES IRQ ? NO YES CGM ? NO OTHER YES ? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR SWI YES ? NO RTI YES UNSTACK CPU REGISTERS ? NO EXECUTE INSTRUCTION Figure 13-5. Interrupt Processing MC68HC908GR16A Data Sheet, Rev. 1.0 SET I BIT Freescale Semiconductor ...
Page 137
... SCI transmitter empty SCI transmission complete Keyboard pin ADC conversion complete Timebase 1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction highest priority Freescale Semiconductor Table 13-1. Interrupt Sources INT Register (1) Flag Mask Flag ...
Page 138
... SS pin goes low at any time with the MODFEN bit set. The error interrupt enable bit, ERRIE, enables MODF CPU interrupt requests. MODF, MODFEN, and ERRIE are in the SPI status and control register. 138 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 139
... The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2–TBR0. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. Freescale Semiconductor MC68HC908GR16A Data Sheet, Rev. 1.0 Interrupts ...
Page 140
... Table 13-2. Interrupt Source Flags Interrupt Status Register Flag IF5 IF4 IF3 IF2 Reserved MC68HC908GR16A Data Sheet, Rev. 1.0 — — IF1 IF2 IF3 IF4 IF5 IF6 IF7 IF8 IF9 IF10 IF11 IF12 IF13 IF14 IF15 IF16 2 1 Bit 0 IF1 Table 13-2. Freescale Semiconductor ...
Page 141
... R Figure 13-8. Interrupt Status Register 3 (INT3) IF16 and IF15 — Interrupt Flags 16 and 15 This flag indicates the presence of an interrupt request from the source shown Interrupt request present interrupt request present Bits 7–2 — Always read 0 Freescale Semiconductor IF13 IF12 IF11 ...
Page 142
... Resets and Interrupts 142 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 143
... ESCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an ESCI input or output reflects the name of the shared port pin. ESCI I/O pins. The generic pin names appear in the text of this section. Freescale Semiconductor Table 14-1 shows the full names and the generic names of the MC68HC908GR16A Data Sheet, Rev ...
Page 144
... PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1 (1), (2) PTC0 PTD7/T2CH1 PTD6/T2CH0 PTD5/T1CH1 PTD4/T1CH0 PTD3/SPSCK PTD2/MOSI PTD1/MISO PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE TxD PTE0/TxD Freescale Semiconductor (1) (1) (1) (1) (1) (1) (1) (1) (1) ...
Page 145
... TCIE SCRIE ILIE TE RE RWU SBK WAKEUP CONTROL BUS CLOCK ENHANCED PRESCALER CGMXCLK ÷ -> SCI_CLK = BUSCLK -> SCI_CLK = CGMSCLK (4x BUSCLK) Figure 14-2. ESCI Module Block Diagram Freescale Semiconductor INTERNAL BUS SCTE TC SCRF OR IDLE LOOPS RECEIVE FLAG CONTROL CONTROL BKF ENSCI RPF PRE- ...
Page 146
... SCP1 SCP0 Unimplemented R MC68HC908GR16A Data Sheet, Rev. 1.0 Figure 14- Bit 0 PSSB3 PSSB2 PSSB1 PSSB0 AFIN ARUN AROVFL ARD8 ARD3 ARD2 ARD1 ARD0 WAKE ILTY PEN PTY RWU SBK ORIE NEIE FEIE PEIE BKF RPF SCR2 SCR1 SCR0 Reserved U = Unaffected Freescale Semiconductor ...
Page 147
... SCP1 SCP0 SCR2 SCR1 SCR0 PEN PDS2 PTY PDS1 PDS0 PSSB4 PSSB3 PSSB2 PSSB1 PSSB0 Freescale Semiconductor PARITY 8-BIT DATA FORMAT OR DATA (BIT M IN SCC1 CLEAR) BIT BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 9-BIT DATA FORMAT (BIT M IN SCC1 SET) BIT 2 ...
Page 148
... Receiving a break character has these effects on ESCI registers: • Sets the framing error bit (FE) in SCS1 • Sets the ESCI receiver full bit (SCRF) in SCS1 • Clears the ESCI data register (SCDR) 148 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 149
... TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. 14.4.3 Receiver Figure 14-6 shows the structure of the ESCI receiver. The receiver I/O registers are summarized in Figure 14-3. Freescale Semiconductor NOTE MC68HC908GR16A Data Sheet, Rev. 1.0 Functional Description 149 ...
Page 150
... DIVIDER DATA RxD RECOVERY ALL ZEROS M WAKEUP LOGIC PARITY CHECKING IDLE ILIE SCRF SCRIE OR ORIE NF NEIE FE FEIE PE PEIE MC68HC908GR16A Data Sheet, Rev. 1.0 ESCI DATA REGISTER 11-BIT RECEIVE SHIFT REGISTER SCRF IDLE R8 ILIE SCRIE OR ORIE NF NEIE FE FEIE PE PEIE Freescale Semiconductor RWU ...
Page 151
... RESET To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 14-2 summarizes the results of the start bit verification samples. RT3, RT5, and RT7 Samples Freescale Semiconductor START BIT START BIT START BIT DATA ...
Page 152
... Data Bit Determination 000 0 001 0 010 0 011 1 100 0 101 1 110 1 111 1 NOTE Table 14-4. Stop Bit Recovery Framing Error Flag 000 1 001 1 010 1 011 0 100 1 101 0 110 0 111 0 MC68HC908GR16A Data Sheet, Rev. 1.0 Noise Flag Table 14-4 Noise Flag Freescale Semiconductor ...
Page 153
... The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10. Freescale Semiconductor MSB DATA SAMPLES Figure 14-8 ...
Page 154
... RT cycles at the point when 154 160 – × 100 = 3.90% ------------------------- - 154 Figure 14-9, the receiver counts 170 RT cycles at the point when 170 176 – × 100 = 3.53% ------------------------- - 170 MC68HC908GR16A Data Sheet, Rev. 1.0 IDLE OR NEXT CHARACTER Freescale Semiconductor ...
Page 155
... The ESCI module is inactive in stop mode. The STOP instruction does not affect ESCI register states. ESCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an ESCI transmission or reception results in invalid data. Freescale Semiconductor NOTE MC68HC908GR16A Data Sheet, Rev. 1.0 Low-Power Modes ...
Page 156
... ESCI status register 2, SCS2 • ESCI data register, SCDR • ESCI baud rate register, SCBR • ESCI prescaler register, SCPSC • ESCI arbiter control register, SCIACTL • ESCI arbiter data register, SCIADAT 156 Support. MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 157
... M — Mode (Character Length) Bit This read/write bit determines whether ESCI characters are eight or nine bits long (See Table 14-5).The ninth bit can serve as a receiver wakeup signal parity bit. Reset clears the M bit 9-bit ESCI characters 0 = 8-bit ESCI characters Freescale Semiconductor ENSCI TXINV ...
Page 158
... Odd 1 8 Even 1 8 Odd Table Table 14-3). Reset clears the PEN bit. NOTE MC68HC908GR16A Data Sheet, Rev. 1.0 Character Length 1 10 bits 1 11 bits 1 10 bits 1 10 bits 1 11 bits 1 11 bits 14-5). When enabled, the parity Freescale Semiconductor ...
Page 159
... Reset clears the TE bit Transmitter enabled 0 = Transmitter disabled Writing to the TE bit is not allowed when the enable ESCI bit (ENSCI) is clear. ENSCI is in ESCI control register 1. Freescale Semiconductor TCIE ...
Page 160
... When the ESCI is receiving 9-bit characters the read-only ninth bit (bit 8) of the received character received at the same time that the SCDR receives the other 8 bits. 160 NOTE NOTE ORIE Unimplemented R = Reserved MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 NEIE FEIE PEIE Unaffected Freescale Semiconductor ...
Page 161
... Receiver input idle • Receiver overrun • Noisy data • Framing error • Parity error Address: $0016 Bit 7 Read: SCTE Write: Reset: 1 Figure 14-13. ESCI Status Register 1 (SCS1) Freescale Semiconductor SCRF IDLE Unimplemented MC68HC908GR16A Data Sheet, Rev. 1.0 I/O Registers 2 1 Bit 0 ...
Page 162
... The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2. 162 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 163
... PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit Parity error detected parity error detected Freescale Semiconductor NORMAL FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 ...
Page 164
... Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018 writes the data to be transmitted, T7:T0. Reset has no effect on the ESCI data register. Do not use read-modify-write instructions on the ESCI data register. 164 Unimplemented Unaffected by reset NOTE MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 0 BKF RPF Bit Freescale Semiconductor ...
Page 165
... This is due to the oscillator tolerance requirement that the slave node must be within ±15% of the master node's oscillator. Since a slave node cannot know running faster or slower than the master node (prior to synchronization), the LINR bit allows the slave Freescale Semiconductor NOTE 6 ...
Page 166
... Table 14-8. ESCI Baud Rate Prescaling Baud Rate Register Prescaler Divisor (BPD Table 14-9. ESCI Baud Rate Selection Baud Rate Divisor (BD 128 NOTE PDS1 PDS0 PSSB4 PSSB3 MC68HC908GR16A Data Sheet, Rev. 1.0 Table 14-8. Reset Table 14-9. Reset clears 2 1 Bit 0 PSSB2 PSSB1 PSSB0 Freescale Semiconductor ...
Page 167
... PSSB[4:3:2:1: Freescale Semiconductor NOTE Table 14-10. ESCI Prescaler Division Ratio Prescaler Divisor (PD) Bypass this prescaler Prescaler Divisor Fine Adjust (PDFA) 0/ 1/32 = 0.03125 2/32 = 0.0625 3/32 = 0.09375 4/32 = 0.125 5/32 = 0.15625 6/32 = 0.1875 7/32 = 0.21875 8/32 = 0.25 9/32 = 0.28125 10/32 = 0.3125 11/32 = 0.34375 12/ ...
Page 168
... Frequency of the SCI clock source 64 x BPD (PD + PDFA) or CGMXCLK (selected by Bus MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 169
... Table 14-12. ESCI Baud Rate Selection Examples PS[2:1:0] PSSB[4:3:2:1: Freescale Semiconductor Prescaler SCP[1:0] Divisor SCR[2:1:0] (BPD MC68HC908GR16A Data Sheet, Rev. 1.0 I/O Registers Baud Rate Baud Rate Divisor (f = 4.9152 MHz) Bus (BD) 1 76,800 1 9600 1 9562.65 1 9525.58 1 8563.07 2 38,400 4 19,200 8 9600 16 4800 ...
Page 170
... This read-only bit indicates the arbiter counter is running. Reset clears ARUN Arbiter counter running 0 = Arbiter counter stopped 170 ALOST AFIN AM0 ACLK Unimplemented ESCI Arbiter Mode Idle / counter reset Bit time measurement Bus arbitration Reserved / do not use NOTE MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 ARUN AROVFL ARD8 Freescale Semiconductor ...
Page 171
... ALOST is set. As long as ALOST is set, the TxD pin is forced to 1, resulting in a seized transmission. If SCI_TxD senses a 0 without having sensed a 0 before on RxD, the counter will be reset, arbitration operation will be restarted after the next rising edge of SCI_TxD. Freescale Semiconductor ...
Page 172
... Enhanced Serial Communications Interface (ESCI) Module RXD Figure 14-21. Bit Time Measurement with ACLK = 0 RXD Figure 14-22. Bit Time Measurement with ACLK = 1, Scenario A RXD Figure 14-23. Bit Time Measurement with ACLK = 1, Scenario B 172 MEASURED TIME MEASURED TIME MEASURED TIME MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 173
... SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing INTERNAL PULLUP DEVICE RESET PIN LOGIC SIM RESET STATUS REGISTER Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL ...
Page 174
... IF5 IF4 IF14 IF13 IF12 IF20 Unimplemented Figure 15-2. SIM I/O Register Summary MC68HC908GR16A Data Sheet, Rev. 1 SBSW (1) Note ILOP ILAD MODRST LVI IF3 IF2 IF1 IF11 IF10 IF9 IF8 IF19 IF18 IF17 IF16 Reserved Freescale Semiconductor Bit IF7 R 0 IF15 R 0 ...
Page 175
... In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Freescale Semiconductor CGMXCLK CGMOUT Figure 15-3 ...
Page 176
... Counter), but an external reset does not. Each of shows the relative timing. VECT H Figure 15-4. External Reset Timing Figure 15-5. An internal reset can be caused by an illegal address, Figure 15-6. NOTE MC68HC908GR16A Data Sheet, Rev. 1.0 15.7 SIM Registers. VECT L Figure 15-5. Freescale Semiconductor ...
Page 177
... The RST pin is driven low during the oscillator stabilization time. • The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. Freescale Semiconductor RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 15-5. Internal Reset Timing ...
Page 178
... The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held 178 32 32 CYCLES CYCLES Figure 15-7. POR Recovery on the RST pin disables the COP module. TST MC68HC908GR16A Data Sheet, Rev. 1.0 $FFFE $FFFF while the MCU is in monitor TST voltage falls to the V DD TRIPF Freescale Semiconductor ...
Page 179
... Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) • Reset • Break interrupts Freescale Semiconductor 15.6.2 Stop Mode 15.3.2 Active Resets from Internal Sources MC68HC908GR16A Data Sheet, Rev. 1.0 SIM Counter 19.3.1.1 Normal Monitor Mode). for details. The SIM counter is ...
Page 180
... SP – – – Figure 15-8 Interrupt Entry Timing SP – – – – 1 [7:0] PC – 1 [15:8] OPCODE Figure 15-9. Interrupt Recovery Timing MC68HC908GR16A Data Sheet, Rev. 1.0 Figure 15-8 shows VECT H VECT L START ADDR CCR V DATA H V DATA L OPCODE OPERAND Freescale Semiconductor ...
Page 181
... CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). See YES AS MANY INTERRUPTS AS EXIST ON CHIP Freescale Semiconductor Figure 15-10. FROM RESET BREAK I BIT SET? ...
Page 182
... A software interrupt pushes PC onto the stack. A software interrupt does not push PC – hardware interrupt does. 182 CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Interrupt Recognition Example . NOTE NOTE MC68HC908GR16A Data Sheet, Rev. 1.0 BACKGROUND ROUTINE Freescale Semiconductor ...
Page 183
... I6–I1 — Interrupt Flags 1–6 These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present Bit 0 and Bit 1 — Always read 0 Freescale Semiconductor Table 15-3. Interrupt Sources Interrupt Source Reset SWI instruction IRQ pin ...
Page 184
... SIM break flag control register (SBFCR). 184 I13 I12 I11 I10 Reserved I20 I19 I18 Reserved MC68HC908GR16A Data Sheet, Rev. 1 Bit Table 15- Bit 0 I17 I16 I15 Table 15-3. TIM2)). The SIM puts the CPU Freescale Semiconductor ...
Page 185
... R/W Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 15-16 and Figure 15-17 Freescale Semiconductor WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 15-15. Wait Mode Entry Timing show the timing for WAIT recovery. MC68HC908GR16A Data Sheet, Rev. 1.0 ...
Page 186
... To minimize stop current, all pins configured as inputs should be driven 186 $6E0B $6E0C $00FF $00FE $A6 $A6 $01 $ CYCLES CYCLES $A6 NOTE Figure 15-18 NOTE MC68HC908GR16A Data Sheet, Rev. 1.0 $00FD $00FC $6E RST VCT H RST VCT L shows stop mode entry timing. Freescale Semiconductor ...
Page 187
... Bit 7 Read: R Write: Reset Writing a 0 clears SBSW. Figure 15-20. Break Status Register (SBSR) Freescale Semiconductor STOP ADDR + 1 PREVIOUS DATA NEXT OPCODE Figure 15-18. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP + 2 STOP + 2 Table 15-4 shows the mapping of these registers. ...
Page 188
... Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ ≠ V TST 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR 188 PIN COP ILOP ILAD MC68HC908GR16A Data Sheet, Rev. 1 Bit 0 MODRST LVI Freescale Semiconductor ...
Page 189
... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Freescale Semiconductor ...
Page 190
... System Integration Module (SIM) 190 MC68HC908GR16A Data Sheet, Rev. 1.0 Freescale Semiconductor ...
Page 191
... If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. The following paragraphs describe the operation of the SPI module. Refer to of the SPI I/O registers. Freescale Semiconductor MC68HC908GR16A Data Sheet, Rev. 1.0 Figure 16-3 for a summary ...
Page 192
... PTA0/KBD0 PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 (1) PTC6 (1) PTC5 (1), (2) PTC4 (1), (2) PTC3 (1), (2) PTC2 (1), (2) PTC1 (1), (2) PTC0 (1) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD4/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE Freescale Semiconductor ...
Page 193
... Reset: Read: SPI Status and Control $0011 Register (SPSCR) Write: See page 208. Reset: Read: SPI Data Register $0012 (SPDR) Write: See page 210. Reset: Freescale Semiconductor INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER RECEIVE DATA REGISTER SPR0 SPMSTR MODFEN SPI ...
Page 194
... NOTE Figure 16-4. MISO MISO MOSI MOSI SPSCK SPSCK Register.) Through the SPSCK pin, the baud rate generator of the MC68HC908GR16A Data Sheet, Rev. 1.0 16.12.1 SPI SLAVE MCU SHIFT REGISTER 16.6.2 Mode Fault Error. Freescale Semiconductor ...
Page 195
... The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select Freescale Semiconductor 16.4 Transmission ...
Page 196
... The SS pin of the master is not shown but is assumed to be inactive. The SS 196 16.6.2 Mode Fault MSB BIT 6 BIT 5 BIT 4 BIT 3 MSB BIT 6 BIT 5 BIT 4 BIT 3 BYTE 1 BYTE 2 Figure 16-6. CPHA/SS Timing MC68HC908GR16A Data Sheet, Rev. 1.0 Error.) When CPHA = 0, the first BIT 2 BIT 1 LSB BIT 2 BIT 1 LSB BYTE 3 Freescale Semiconductor ...
Page 197
... Figure 16-8. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. Freescale Semiconductor ...
Page 198
... POSSIBLE START POINTS LATEST SPSCK = BUS CLOCK ÷ 8; EARLIEST 8 POSSIBLE START POINTS SPSCK = BUS CLOCK ÷ 32; EARLIEST 32 POSSIBLE START POINTS SPSCK = BUS CLOCK ÷ 128; EARLIEST 128 POSSIBLE START POINTS MC68HC908GR16A Data Sheet, Rev. 1.0 BIT 6 BIT LATEST LATEST LATEST Freescale Semiconductor ...
Page 199
... For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. SPTE indicates when the next write can occur. Freescale Semiconductor 3 5 ...
Page 200
... CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT, BUT NOT OVRF BIT. 8 BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST. MC68HC908GR16A Data Sheet, Rev. 1.0 16-7 overflow occurs, all data Figure 16-12.) It Figure 16-10 shows how it is BYTE 4 8 Freescale Semiconductor ...