MC908GR16AVFAE Freescale Semiconductor, MC908GR16AVFAE Datasheet - Page 159
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MC908GR16AVFAE
Manufacturer Part Number
MC908GR16AVFAE
Description
IC MCU 8BIT 16K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR16ACFAE.pdf
(270 pages)
Specifications of MC908GR16AVFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR16AVFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC908GR16AVFAER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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SCTIE — ESCI Transmit Interrupt Enable Bit
TCIE — Transmission Complete Interrupt Enable Bit
SCRIE — ESCI Receive Interrupt Enable Bit
ILIE — Idle Line Interrupt Enable Bit
TE — Transmitter Enable Bit
Freescale Semiconductor
•
•
•
•
This read/write bit enables the SCTE bit to generate ESCI transmitter CPU interrupt requests. Setting
the SCTIE bit in SCC2 enables the SCTE bit to generate CPU interrupt requests. Reset clears the
SCTIE bit.
This read/write bit enables the TC bit to generate ESCI transmitter CPU interrupt requests. Reset
clears the TCIE bit.
This read/write bit enables the SCRF bit to generate ESCI receiver CPU interrupt requests. Setting the
SCRIE bit in SCC2 enables the SCRF bit to generate CPU interrupt requests. Reset clears the
SCRIE bit.
This read/write bit enables the IDLE bit to generate ESCI receiver CPU interrupt requests. Reset clears
the ILIE bit.
Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 1s from the
transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the TxD returns to the idle condition (1). Clearing and then setting TE
during a transmission queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
1 = Transmitter enabled
0 = Transmitter disabled
Enables the transmitter
Enables the receiver
Enables ESCI wakeup
Transmits ESCI break characters
Address: $0014
Writing to the TE bit is not allowed when the enable ESCI bit (ENSCI) is
clear. ENSCI is in ESCI control register 1.
Reset:
Read:
Write:
SCTIE
Bit 7
0
Figure 14-11. ESCI Control Register 2 (SCC2)
TCIE
6
0
MC68HC908GR16A Data Sheet, Rev. 1.0
SCRIE
5
0
NOTE
ILIE
4
0
TE
3
0
RE
2
0
RWU
1
0
Bit 0
SBK
0
:
I/O Registers
159
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