MC908GR16AVFAE Freescale Semiconductor, MC908GR16AVFAE Datasheet - Page 160
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MC908GR16AVFAE
Manufacturer Part Number
MC908GR16AVFAE
Description
IC MCU 8BIT 16K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR16ACFAE.pdf
(270 pages)
Specifications of MC908GR16AVFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR16AVFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC908GR16AVFAER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Enhanced Serial Communications Interface (ESCI) Module
RE — Receiver Enable Bit
RWU — Receiver Wakeup Bit
SBK — Send Break Bit
14.8.3 ESCI Control Register 3
ESCI control register 3 (SCC3):
R8 — Received Bit 8
160
Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not
affect receiver interrupt flag bits. Reset clears the RE bit.
This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled.
The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out
of the standby state and clears the RWU bit. Reset clears the RWU bit.
Setting and then clearing this read/write bit transmits a break character followed by a 1. The 1 after the
break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter
continuously transmits break characters with no 1s between them. Reset clears the SBK bit.
•
•
When the ESCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received
character. R8 is received at the same time that the SCDR receives the other 8 bits.
1 = Receiver enabled
0 = Receiver disabled
1 = Standby state
0 = Normal operation
1 = Transmit break characters
0 = No break characters being transmitted
Stores the ninth ESCI data bit received and the ninth ESCI data bit to be transmitted.
Enables these interrupts:
–
–
–
–
Receiver overrun
Noise error
Framing error
Parity error
Address:
Writing to the RE bit is not allowed when the enable ESCI bit (ENSCI) is
clear. ENSCI is in ESCI control register 1.
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling
SBK before the preamble begins causes the ESCI to send a break
character instead of a preamble.
Reset:
Read:
Write:
$0015
Bit 7
R8
U
Figure 14-12. ESCI Control Register 3 (SCC3)
= Unimplemented
T8
6
0
MC68HC908GR16A Data Sheet, Rev. 1.0
R
5
0
NOTE
NOTE
R
R
4
0
= Reserved
ORIE
3
0
NEIE
U = Unaffected
2
0
FEIE
1
0
Freescale Semiconductor
PEIE
Bit 0
0
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