M38503G4AFP#U1 Renesas Electronics America, M38503G4AFP#U1 Datasheet - Page 15

• Manufacturer Part Number: M38503G4AFP#U1
• Description: IC 740/3850 MCU QZ-ROM 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38503G4AFP#U1

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: QzROM
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3850 Group (Spec.A QzROM version)
Rev.2.13
REJ03B0125-0213
I/O PORTS
The I/O ports have direction registers which determine the
input/output direction of each individual pin. Each bit in a
direction register corresponds to one pin, and each pin can be set
to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Table 7
NOTES:
P0
P0
P0
P0
P0
P0
P1
P2
P2
P2
P2
P2
P2
P2
P2
S
P3
P3
P4
P4
P4
P4
S
P4
PWM
RDY1
CMP2
1. When bits 5 to 7 of Ports P3 and P4 are read out, the contents are undefined.
0
1
2
3
4
7
0
0
1
2
3
4
5
6
7
0
4
0
1
2
3
4
/S
/S
/S
/S
/AN
/AN
− P1
/X
/X
/R
/T
/S
/CNTR
/AN
/AN
/CNTR
/INT
/INT
/INT
/INT
X
IN2
OUT2
CLK2
RDY2
COUT
CIN
CLK1
X
Pin
D
D
5
8
0
4
7
0
1
2
3
−
−
/
/
0
1
/
I/O port function
Apr 17, 2009
Port P0
Port P1
Port P2
Port P3
Port P4
Name
(1)
(1)
Input/out
put,
individual
bits
Input/Out
put
Page 13 of 56
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
N-channel open-drain
output
CMOS compatible input
level
CMOS 3-state output
I/O Structure
Serial I/O2 function I/O
A/D converter input
Sub-clock generating
circuit
Serial I/O1 function I/O
Serial I/O1 function I/O
Timer X function I/O
A/D converter input
Timer Y function I/O
External interrupt input
External interrupt input
S
External interrupt input
PWM output
CMP2
By setting the port P0, P1, P2 pull-up control register (address
0012
the port P4 pull-up control register (address 0014
control pull-up with a program. However, the contents of these
registers do not affect ports programmed as the output ports.
Non-Port Function
output
16
), the port P3 pull-up control register (address 0013
Serial I/O2 control register
AD control register
AD input selection register
CPU mode register
Serial I/O1 control register
Serial I/O1 control register
Timer XY mode register
AD control register
AD input selection register
Timer XY mode register
Interrupt edge selection register
Interrupt edge selection register
Serial I/O2 control register
Interrupt edge selection register
PWM control register
Related SFRs
16
), ports can
Ref.No.
(13)
(10)
(12)
(13)
(14)
(15)
(16)
(17)
(11)
16
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
), or