M38503G4AFP#U1 Renesas Electronics America, M38503G4AFP#U1 Datasheet - Page 5

• Manufacturer Part Number: M38503G4AFP#U1
• Description: IC 740/3850 MCU QZ-ROM 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38503G4AFP#U1

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: QzROM
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3850 Group (Spec.A QzROM version)
Rev.2.13
REJ03B0125-0213
PIN DESCRIPTION
Table 1
V
CNV
V
AV
RESET
X
X
P0
P0
P0
P0
P0
P1
P2
P2
P2
P2
P2
P2
P2
P2
P3
P4
P4
P4
P4
P4
CC
REF
IN
OUT
SS
0
1
2
3
4
0
0
1
2
3
4
5
6
7
0
0
1
2
3
4
/S
/S
/S
/S
/AN
-P1
/X
/X
/R
/T
/S
/CNTR
/AN
/CNTR
/INT
/INT
/INT
/INT
, V
SS
X
IN2
OUT2
CLK2
RDY2
COUT
CIN
CLK1
X
SS
D
7
D
Pin
5
0
0
1
2
3
−P0
−P3
/S
/PWM
0
1
CMP2
Pin description
/S
7
4
/AN
/AN
Apr 17, 2009
RDY1
8
4
Power source
CNV
Reference
voltage
Analog power
source
Reset input
Clock input
Clock output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
SS
Name
input
Page 3 of 56
Apply voltage of 1.8 V−5.5 V to V
• This pin controls the operation mode of the chip and is shared with the V
• Normally connected to V
Reference voltage input pin for A/D converter.
• Analog power source input pin for A/D converter.
• Connect to V
• Reset input pin for active “L”.
• Input and output pins for the clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the X
• When an external clock is used, connect the clock source to the X
• 8-bit CMOS I/O port.
• I/O direction register allows each pin to be individually
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled in a byte unit.
• P1
• 8-bit CMOS I/O port.
• I/O direction register allows each pin to be individually
• CMOS compatible input level.
• P2
• P2
• Pull-up control of P2
• 5-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled in a bit unit.
• 5-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled in a bit unit.
power source input pin for programming the built-in QzROM.
the oscillation frequency.
open.
programmed as either input or output.
for LED drive.
programmed as either input or output.
byte unit.
0
0
2
, P2
, P2
to P1
1
3
, P2
: N-channel open-drain structure.
7
(8 bits) are enabled to output large current
4
SS
, to P2
.
7
0
: CMOS3-state output structure.
, P2
Function
SS
1
, P2
.
4
−P2
CC
, and 0 V to V
7
is enabled in a
SS
.
• Serial I/O2 function pin
• A/D converter input pin
• Sub-clock generating circuit I/O
• Serial I/O1 function pin
• Serial I/O1 function pin
• Timer X function pin
• A/D converter input pin
• Timer Y function pin
• Interrupt input pins
• Interrupt input pin
• S
• Interrupt input pin
• PWM output pin
pins (connect a resonator)
CMP2
Function except a port function
IN
output pin
pin and leave the X
IN
PP
and X
pin which is the
OUT
pins to set
OUT
pin