MC908GR4CDWE Freescale Semiconductor, MC908GR4CDWE Datasheet - Page 153

IC MCU 4K FLASH 8MHZ 28-SOIC

MC908GR4CDWE

Manufacturer Part Number
MC908GR4CDWE
Description
IC MCU 4K FLASH 8MHZ 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheets

Specifications of MC908GR4CDWE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
384Byte
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8.2 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
MC68HC908GR8 — Rev 4.0
MOTOROLA
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
SEC
SEI
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
STHX opr
STOP
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
SWI
TAP
TAX
TPA
Source
Form
Subtract with Carry
Set Carry Bit
Set Interrupt Mask
Store A in M
Store H:X in M
Enable IRQ Pin; Stop Oscillator
Store X in M
Subtract
Software Interrupt
Transfer A to CCR
Transfer A to X
Transfer CCR to A
Operation
Table 10-1. Instruction Set Summary (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
Central Processing Unit (CPU)
Go to: www.freescale.com
PCH
PCL
PC
SP
SP
SP
SP
I
SP
A
(M:M + 1)
Interrupt Vector High Byte
Interrupt Vector Low Byte
Description
(SP) – 1; Push (CCR)
(SP) – 1; Push (PCH)
(PC) + 1; Push (PCL)
A
0; Stop Oscillator
(SP) – 1; Push (X)
(SP) – 1; Push (A)
CCR
A
(A) – (M) – (C)
M
M
(SP) – 1; I
X
C
I
(A) – (M)
(CCR)
(A)
(A)
(X)
1
1
(A)
(H:X)
1
V H I N Z C
– – – – – 1 INH
– – 1 – – – INH
0 – –
0 – –
– – 0 – – – INH
0 – –
– – 1 – – – INH
– – – – – – INH
– – – – – – INH
Effect on
– –
– –
CCR
Central Processing Unit (CPU)
Instruction Set Summary
– DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
INH
Technical Data
9EDF
9EE2
9ED2
9EE7
9ED7
9EEF
9EE0
9ED0
C2
D2
C7
D7
BF
CF
DF
EF
C0
D0
A2
B2
E2
F2
99
9B
B7
E7
F7
35
8E
FF
A0
B0
E0
F0
83
84
97
85
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
dd
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
153
2
3
4
4
3
2
4
5
1
2
3
4
4
3
2
4
5
4
1
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
9
2
1
1

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