MC908AP32ACFBER Freescale Semiconductor, MC908AP32ACFBER Datasheet - Page 149

• Manufacturer Part Number: MC908AP32ACFBER
• Description: IC MCU 32K FLASH 8MHZ 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32ACFBER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Processor Series: HC08AP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908AP64E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TBR[2:0] — Timebase Rate Selection
TACK — Timebase ACKnowledge
TBIE — Timebase Interrupt Enabled
TBON — Timebase Enabled
Freescale Semiconductor
These read/write bits are used to select the rate of timebase interrupts as shown in
The TACK bit is a write-only bit and always reads as 0. Writing a logic 1 to this bit clears TBIF, the
timebase interrupt flag bit. Writing a logic 0 to this bit has no effect.
This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the
TBIE bit.
This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption
when its function is not necessary. The counter can be initialized by clearing and then setting this bit.
Reset clears the TBON bit.
1 = Clear timebase interrupt flag
0 = No effect
1 = Timebase interrupt enabled
0 = Timebase interrupt disabled
1 = Timebase enabled
0 = Timebase disabled and the counter initialized to 0’s
1. If user selects one of the shaded timebase settings, ensure that the operating bus
TBR2
Do not change TBR[2:0] bits while the timebase is enabled (TBON = 1).
frequency is fast enough to service the periodic interrupts.
0
0
0
0
1
1
1
1
Table 10-1. Timebase Rate Selection for OSCCLK = 4 MHz
TBR1
0
0
1
1
0
0
1
1
MC68HC908AP A-Family Data Sheet, Rev. 3
TBR0
0
1
0
1
0
1
0
1
Divider
262144
131072
65536
32768
NOTE
64
32
16
8
125,000
250,000
500,000
15.259
30.518
61.035
122.07
62,500
Timebase Interrupt Rate
Hz
Timebase Register Description
65.536
32.768
16.384
8.192
0.016
0.008
0.004
0.002
ms
(1)
Table
10-1.
149