MC9S08RG60CFGE Freescale Semiconductor, MC9S08RG60CFGE Datasheet - Page 133
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MC9S08RG60CFGE
Manufacturer Part Number
MC9S08RG60CFGE
Description
IC MCU 60K FLASH 8MHZ 44LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08RE8FJE.pdf
(234 pages)
Specifications of MC9S08RG60CFGE
Core Processor
HCS08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
S08RG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
39
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08RG60E
Minimum Operating Temperature
- 40 C
Controller Family/series
HCS08
No. Of I/o's
39
Ram Memory Size
60KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
For Use With
DEMO9S08RG60E - BOARD DEMO S08RG/RC/RD/RE FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08RG60CFGE
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MC9S08RG60CFGE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Timer/PWM (TPM)
independently be configured to operate in input capture, output compare, or buffered edge-aligned PWM
mode.
The following sections describe the main 16-bit counter and each of the timer operating modes (input
capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation
and interrupt activity depend on the operating mode, these topics are covered in the associated mode
sections.
10.5.1
Counter
All timer functions are based on the main 16-bit counter (TPM1CNTH:TPM1CNTL). This section
discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count overflow, and
manual counter reset.
After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM is inactive.
Normally, CLKSB:CLKSA would be set to 0:1 so the bus clock drives the timer counter. The clock source
for the TPM can be selected to be off, the bus clock (BUSCLK), the fixed system clock (XCLK), or an
external input through the TPM1CH0 pin. The maximum frequency allowed for the external clock option
is one-fourth the bus rate. Refer to
Section 10.7.1, “Timer Status and Control Register
(TPM1SC),” and
Table 10-2
for more information about clock source selection.
When the microcontroller is in active background mode, the TPM temporarily suspends all counting until
the microcontroller returns to normal user operating mode. During stop mode, all TPM clocks are stopped;
therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to
operate normally.
The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1),
the counter operates in up-/down-counting mode. Otherwise, the counter operates as a simple up-counter.
As an up-counter, the main 16-bit counter counts from $0000 through its terminal count and then continues
with $0000. The terminal count is $FFFF or a modulus value in TPM1MODH:TPM1MODL.
When center-aligned PWM operation is specified, the counter counts upward from $0000 through its
terminal count and then counts downward to $0000 where it returns to up-counting. Both $0000 and the
terminal count value (value in TPM1MODH:TPM1MODL) are normal length counts (one timer clock
period long).
An interrupt flag and enable are associated with the main 16-bit counter. The timer overflow flag (TOF) is
a software-accessible indication that the timer counter has overflowed. The enable signal selects between
software polling (TOIE = 0) where no hardware interrupt is generated, or interrupt-driven operation
(TOIE = 1) where a static hardware interrupt is automatically generated whenever the TOF flag is 1.
The conditions that cause TOF to become set depend on the counting mode (up or up/down). In
up-counting mode, the main 16-bit counter counts from $0000 through $FFFF and overflows to $0000 on
the next counting clock. TOF becomes set at the transition from $FFFF to $0000. When a modulus limit
is set, TOF becomes set at the transition from the value set in the modulus register to $0000. When the
main 16-bit counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes
direction at the transition from the value set in the modulus register and the next lower count value. This
corresponds to the end of a PWM period. (The $0000 count value corresponds to the center of a period.)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
133