MC9S08RG60CFGE Freescale Semiconductor, MC9S08RG60CFGE Datasheet - Page 158
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MC9S08RG60CFGE
Manufacturer Part Number
MC9S08RG60CFGE
Description
IC MCU 60K FLASH 8MHZ 44LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08RE8FJE.pdf
(234 pages)
Specifications of MC9S08RG60CFGE
Core Processor
HCS08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
S08RG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
39
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08RG60E
Minimum Operating Temperature
- 40 C
Controller Family/series
HCS08
No. Of I/o's
39
Ram Memory Size
60KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
For Use With
DEMO9S08RG60E - BOARD DEMO S08RG/RC/RD/RE FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08RG60CFGE
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MC9S08RG60CFGE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Serial Communications Interface (S08SCIV1)
the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the
transmit data register empty (TDRE) status flag is set to indicate another character may be written to the
transmit data buffer at SCI1D.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD1 pin, the
transmitter sets the transmit complete flag and enters an idle mode, with TxD1 high, waiting for more
characters to transmit.
Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity
that is in progress must first be completed. This includes data characters in progress, queued idle
characters, and queued break characters.
12.3.2.1
Send Break and Queued Idle
The SBK control bit in SCI1C2 is used to send break characters which were originally used to gain the
attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times
including the start and stop bits). Normally, a program would wait for TDRE to become set to indicate the
last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the SBK bit.
This action queues a break character to be sent as soon as the shifter is available. If SBK is still 1 when the
queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is
queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be
received as 0s in all eight data bits and a framing error (FE = 1) occurs.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake
up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last
character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This
action queues an idle character to be sent as soon as the shifter is available. As long as the character in the
shifter does not finish while TE = 0, the SCI transmitter never actually releases control of the TxD1 pin. If
there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin
that is shared with TxD1 is an output driving a logic 1. This ensures that the TxD1 line will look like a
normal idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE.
12.3.3
Receiver Functional Description
In this section, the data sampling technique used to reconstruct receiver data is described in more detail;
two variations of the receiver wakeup function are explained. (The receiver block diagram is shown in
Figure
12-2.)
The receiver is enabled by setting the RE bit in SCI1C2. Character frames consist of a start bit of logic 0,
eight (or nine) data bits (LSB first), and a stop bit of logic 1. For information about 9-bit data mode, refer
to
Section 12.3.5.1, “8- and 9-Bit Data
Modes.” For the remainder of this discussion, we assume the SCI
is configured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already full,
the data character is transferred to the receive data register and the receive data register full (RDRF) status
flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun
(OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
158
Freescale Semiconductor