MCF51CN128CGT Freescale Semiconductor, MCF51CN128CGT Datasheet - Page 14
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MCF51CN128CGT
Manufacturer Part Number
MCF51CN128CGT
Description
IC MCU 32BIT 128K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
MCF51CNr
Specifications of MCF51CN128CGT
Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, SCI, SPI
Peripherals
LVD, PWM, WDT
Number Of I /o
38
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
MCF51CN
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
24 KB
Interface Type
I2C, SPI, SCI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
38
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 12 Channel
For Use With
TWR-MCF51CN - KIT TOWER BOARDTWR-MCF51CN-KIT - KIT TOWER BOARD/SERIAL/ELEVATOR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF51CN128CGT
Manufacturer:
CIRRUS
Quantity:
1 355
Electrical Characteristics
3.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
14
ESD Protection and Latch-Up Immunity
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
No.
Machine
Latch-up
1
2
3
4
Human
Model
Body
Human body model (HBM)
Machine model (MM)
Charge device model (CDM)
Latch-up current at T
Series resistance
Storage capacitance
Number of pulses per pin
Series resistance
Storage capacitance
Number of pulses per pin
Minimum input voltage limit
Maximum input voltage limit
Table 7. ESD and Latch-Up Protection Characteristics
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Table 6. ESD and Latch-up Test Conditions
Rating
Description
1
A
= 85°C
Symbol
V
V
V
I
HBM
CDM
LAT
MM
Symbol
R1
R1
—
—
—
—
C
C
± 2000
± 200
± 500
± 100
Min
Value
1500
– 2.5
100
200
7.5
3
0
3
Max
—
—
—
—
Freescale Semiconductor
Unit
pF
pF
Ω
Ω
V
V
Unit
mA
V
V
V