MC9S12XET256MAA Freescale Semiconductor, MC9S12XET256MAA Datasheet - Page 387

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MC9S12XET256MAA

Manufacturer Part Number
MC9S12XET256MAA
Description
MCU 16BIT 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XET256MAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 12x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-QFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
59
Number Of Timers
25
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Package
80PQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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10.8.1.13 Index Register plus Register Offset (IDR)
For load and store instructions (RS, RI) provides a variable offset in a register.
Examples:
10.8.1.14 Index Register plus Register Offset with Post-increment (IDR+)
[RS, RI+] provides a variable offset in a register, which is incremented after accessing the memory. In case
of a byte access the index register will be incremented by one. In case of a word access it will be
incremented by two.
Examples:
10.8.1.15 Index Register plus Register Offset with Pre-decrement (–IDR)
[RS, -RI] provides a variable offset in a register, which is decremented before accessing the memory. In
case of a byte access the index register will be decremented by one. In case of a word access it will be
decremented by two.
Examples:
10.8.2
10.8.2.1
Any register can be loaded either with an immediate or from the address space using indexed addressing
modes.
The same set of modes is available for the store instructions
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
LDB
STW
LDB
STW
LDB
STW
LDL
LDW
LDB
STB
STW
Instruction Summary and Usage
Load & Store Instructions
R4,(R1,R2)
R4,(R1,R2)
R4,(R1,R2+)
R4,(R1,R2+)
R4,(R1,-R2)
R4,(R1,-R2)
RD,#IMM8
RD,(RB,RI)
RD,(RB, RI+)
RS,(RB, RI)
RS,(RB, RI+)
MC9S12XE-Family Reference Manual Rev. 1.23
; loads a byte from (R1+R2) into R4
; stores R4 as a word to (R1+R2)
; loads a byte from (R1+R2) into R4, R2+=1
; stores R4 as a word to (R1+R2), R2+=2
; R2 -=1, loads a byte from (R1+R2) into R4
; R2 -=2, stores R4 as a word to (R1+R2)
; loads an immediate 8 bit value to the lower byte of RD
; loads data using RB+RI as effective address
; loads data using RB+RI as effective address
; followed by an increment of RI depending on
; the size of the operation
; stores data using RB+RI as effective address
; stores data using RB+RI as effective address
; followed by an increment of RI depending on
; the size of the operation.
Chapter 10 XGATE (S12XGATEV3)
387

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