R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 220
![MCU 1KB FLASH 32K ROM 48-LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
R5F21346CNFP#U0
Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet
1.R5F21346CNFPU0.pdf
(759 pages)
Specifications of R5F21346CNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 187 of 723
14.2
14.2.1
Note:
14.2.2
Note:
14.2.3
b7 to b0 Writing 00h and then FFh to this register initializes the watchdog timer.
b7 to b0 A write instruction to this register starts the watchdog timer.
After Reset
1. The PM12 bit is set to 1 when 1 is written by a program (and remains unchanged even if 0 is written to it).
After Reset
1. Write the WDTR register during the count operation of the watchdog timer.
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
Bit
Address 0005h
Address 000Dh
Address 000Eh
This bit is automatically set to 1 when the CSPRO bit in the CSPR register is set to 1 (count source protection
mode enabled).
Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM1 register.
Symbol
Symbol
Symbol
Registers
Symbol
The initial value of the watchdog timer is specified by bits WDTUFS0 and WDTUF1 in the OFS2
register.
Bit
Bit
Bit
PM12
Processor Mode Register 1 (PM1)
Watchdog Timer Reset Register (WDTR)
Watchdog Timer Start Register (WDTS)
—
—
—
—
—
—
—
b7
b7
b7
—
—
—
X
X
0
(1)
Reserved bits
WDT interrupt/reset switch bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Reserved bit
b6
b6
b6
—
—
—
X
X
0
Bit Name
b5
—
b5
—
b5
—
X
X
0
b4
b4
b4
—
—
—
X
X
0
Set to 0.
0: Watchdog timer interrupt
1: Watchdog timer reset
Set to 0.
Function
Function
b3
b3
b3
—
—
—
0
X
X
PM12
b2
b2
b2
—
—
X
X
0
Function
(1)
b1
b1
b1
—
—
—
X
X
0
b0
b0
b0
—
—
—
X
X
0
14. Watchdog Timer
R/W
R/W
R/W
R/W
R/W
R/W
—
W
W
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