R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 364

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 331 of 723
20.4.4
Notes:
After Reset
1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit.
2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit.
3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0137h
stops).
stops).
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 20.10.1
TRDSTR Register of Notes on Timer RD.
Symbol
TSTART0 TRD0 count start flag
TSTART1 TRD1 count start flag
Bit
Symbol
CSEL0
CSEL1
Timer RD Start Register (TRDSTR) in Output Compare Function
—
—
—
—
b7
—
1
TRD0 count operation select bit
TRD1 count operation select bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
b6
—
1
Bit Name
b5
—
1
(3)
(4)
b4
—
1
CSEL1
0: Count stops
1: Count starts
0: Count stops
1: Count starts
0: Count stops at the compare match with the
1: Count continues after the compare match with
0: Count stops at the compare match with the
1: Count continues after the compare match with
b3
1
TRDGRA0 register
the TRDGRA0 register
TRDGRA1 register
the TRDGRA1 register
CSEL0 TSTART1 TSTART0
b2
1
(1)
(2)
Function
b1
0
b0
0
20. Timer RD
R/W
R/W
R/W
R/W
R/W
—