C8051F34C-GQ Silicon Laboratories Inc, C8051F34C-GQ Datasheet - Page 162
C8051F34C-GQ
Manufacturer Part Number
C8051F34C-GQ
Description
IC 8051 MCU 64K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Specifications of C8051F34C-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.25 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Ram Size
256 KB
Interface Type
UART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F34C-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F34C-GQR
Manufacturer:
Silicon Laboratories Inc
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16.3. USB Register Access
The USB0 controller registers listed in Table 16.2 are accessed through two SFRs: USB0 Address
(USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted
by reads/writes of the USB0DAT register. See Figure 16.2.
Endpoint control/status registers are accessed by first writing the USB register INDEX with the target end-
point number. Once the target endpoint number is written to the INDEX register, the control/status registers
associated with the target endpoint may be accessed. See the “Indexed Registers” section of Table 16.2
for a list of endpoint control/status registers.
Important Note: The USB clock must be active when accessing USB registers.
162
USB0DAT
USB0ADR
SFRs
8051
Figure 16.2. USB0 Register Access Scheme
Rev. 1.3
Registers
Registers
Common
Interrupt
Register
Access
Index
FIFO
USB Controller
Endpoint0 Control/
Endpoint1 Control/
Endpoint2 Control/
Endpoint3 Control/
Status Registers
Status Registers
Status Registers
Status Registers
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