C8051F34C-GQ Silicon Laboratories Inc, C8051F34C-GQ Datasheet - Page 231

• Manufacturer Part Number: C8051F34C-GQ
• Description: IC 8051 MCU 64K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F34xr

Specifications of C8051F34C-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Ram Size: 256 KB
• Interface Type: UART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F340DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bits 7–0: SCR7–SCR0: SPI0 Clock Rate.
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
f
Bits 7–0: SPI0DAT: SPI0 Transmit and Receive Data.
SCK
SCR7
f
SCK
R/W
Bit7
R/W
Bit7
=
=
These bits determine the frequency of the SCK output when the SPI0 module is configured
for master mode operation. The SCK clock frequency is a divided version of the system
clock, and is given in the following equation, where SYSCLK is the system clock frequency
and SPI0CKR is the 8-bit value held in the SPI0CKR register.
for 0 <= SPI0CKR <= 255
f
200kHz
SCK
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT
places the data into the transmit buffer and initiates a transfer when in Master Mode. A read
of SPI0DAT returns the contents of the receive buffer.
------------------------- -
2
2000000
SCR6

R/W
Bit6

=
R/W
Bit6
4
+
------------------------------------------------ -
2

1
SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate


SPI0CKR
SCR5
SYSCLK
R/W
Bit5
SFR Definition 20.4. SPI0DAT: SPI0 Data
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
SCR4
+
R/W
Bit4
1
R/W
Bit4

SCR3
Rev. 1.3
R/W
Bit3
R/W
Bit3
SCR2
R/W
Bit2
R/W
Bit2
SCR1
R/W
Bit1
R/W
Bit1
SFR Address: 0xA2
SFR Address: 0xA3
SCR0
R/W
Bit0
R/W
Bit0
00000000
Reset Value
00000000
Reset Value
231