C8051F34C-GQ Silicon Laboratories Inc, C8051F34C-GQ Datasheet - Page 205
C8051F34C-GQ
Manufacturer Part Number
C8051F34C-GQ
Description
IC 8051 MCU 64K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Specifications of C8051F34C-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.25 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Ram Size
256 KB
Interface Type
UART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F34C-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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Part Number:
C8051F34C-GQR
Manufacturer:
Silicon Laboratories Inc
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18. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in
UART0 to start reception of a second incoming data byte before software has finished reading the previous
data byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
Section “18.1. Enhanced Baud Rate Generation” on page 206
Rate Generator
UART0 Baud
Write to
SBUF0
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Figure 18.1. UART0 Block Diagram
Rx Clock
Start
Tx Clock
Start
Stop Bit
SBUF0
Read
SCON
TB80
D
SET
CLR
Shift
Input Shift Register
Q
Shift
SFR Bus
(RX Latch)
SBUF0
Tx Control
Rx Control
(9 bits)
0x1FF
SFR Bus
Zero Detector
(TX Shift)
SBUF0
RB80
Load SBUF0
Rev. 1.3
Tx IRQ
Rx IRQ
RI0
TI0
SBUF0
Load
Data
Send
Interrupt
Serial
Port
RX0
TX0
). Received data buffering allows
Crossbar
Crossbar
Port I/O
205
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