MC9S08GT60CFD Freescale Semiconductor, MC9S08GT60CFD Datasheet - Page 100

• Manufacturer Part Number: MC9S08GT60CFD
• Description: MCU 8BIT 60K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT60CFD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Internal Clock Generator (ICG) Module
The module is intended to be very user friendly with many of the features occurring automatically without
user intervention. To quickly configure the module, go to
Information,” and pick an example that best suits the application needs.
7.1.1
Features of the ICG and clock distribution system:
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Frequency-locked loop — A frequency-locked loop (FLL) stage takes either the internal or
external clock source and multiplies it to a higher frequency. Status bits provide information when
the circuit has achieved lock and when it falls out of lock. Additionally, this block can monitor the
external reference clock and signals whether the clock is valid or not.
Clock select block — The clock select block provides several switch options for connecting
different clock sources to the system clock tree. ICGDCLK is the multiplied clock frequency out
of the FLL, ICGERCLK is the reference clock frequency from the crystal or external clock source,
and FFE (fixed frequency enable) is a control signal used to control the system fixed frequency
clock (XCLK). ICGLCLK is the clock source for the background debug controller (BDC).
Several options for the primary clock source allow a wide range of cost, frequency, and precision
choices:
— 32 kHz–100 kHz crystal or resonator
— 1 MHz–16 MHz crystal or resonator
— External clock
— Internal reference generator
Defaults to self-clocked mode to minimize startup delays
Frequency-locked loop (FLL) generates 8 MHz to 40 MHz (for bus rates up to 20 MHz)
— Uses external or internal clock as reference frequency
Automatic lockout of non-running clock sources
Reset or interrupt on loss of clock or loss of FLL lock
Digitally-controlled oscillator (DCO) preserves previous frequency settings, allowing fast
frequency lock when recovering from stop3 mode
DCO will maintain operating frequency during a loss or removal of reference clock
Post-FLL divider selects 1 of 8 bus rate divisors (/1 through /128)
Separate self-clocked source for real-time interrupt
Trimmable internal clock source supports SCI communications without additional external
components
Automatic FLL engagement after lock is acquired
Features
MC9S08GB/GT Data Sheet, Rev. 2.3
Section 7.4, “Initialization/Application
Freescale Semiconductor