MC9S08GT60CFD Freescale Semiconductor, MC9S08GT60CFD Datasheet - Page 163

• Manufacturer Part Number: MC9S08GT60CFD
• Description: MCU 8BIT 60K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT60CFD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

When background mode is active, the timer counter and the coherency mechanism are frozen such that the
buffer latches remain in the state they were in when the background mode became active even if one or
both bytes of the counter are read while background mode is active.
10.7.3
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from $0000 at the next clock
(CPWMS = 0) or starts counting down (CPWMS = 1), and the overflow flag (TOF) becomes set. Writing
to TPMxMODH or TPMxMODL inhibits the TOF bit and overflow interrupts until the other byte is
written. Reset sets the TPM counter modulo registers to $0000, which results in a free-running timer
counter (modulo disabled).
It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well
before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM
modulo registers to avoid confusion about when the first counter overflow will occur.
10.7.4
TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the
interrupt enable, channel configuration, and pin function.
Freescale Semiconductor
Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL)
Timer x Channel n Status and Control Register (TPMxCnSC)
Figure 10-10. Timer x Channel n Status and Control Register (TPMxCnSC)
Figure 10-8. Timer x Counter Modulo Register High (TPMxMODH)
Figure 10-9. Timer x Counter Modulo Register Low (TPMxMODL)
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 15
CHnF
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
= Unimplemented or Reserved
MC9S08GB/GT Data Sheet, Rev. 2.3
CHnIE
14
6
0
6
6
0
6
0
MSnB
13
5
0
5
5
0
5
0
MSnA
12
4
0
4
4
0
4
0
ELSnB
11
3
0
3
3
0
3
0
ELSnA
10
3
0
2
2
0
2
0
TPM Registers and Control Bits
0
2
9
0
1
1
0
1
0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
0
0
0
0
163