MC9S12C96CFUE Freescale Semiconductor, MC9S12C96CFUE Datasheet - Page 136
![IC MCU 96K FLASH 4K RAM 80-QFP](/photos/12/37/123774/mc9s12c96cfue_sml.jpg)
MC9S12C96CFUE
Manufacturer Part Number
MC9S12C96CFUE
Description
IC MCU 96K FLASH 4K RAM 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C96CFUE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
60
Number Of Timers
8
Operating Supply Voltage
- 0.3 V to + 6.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C96CFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC9S12C96CFUER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 4 Multiplexed External Bus Interface (MEBIV3)
4.3.2.3
Read: Anytime when register is in the map
Write: Anytime when register is in the map
This register controls the data direction for port A. When port A is operating as a general-purpose I/O port,
DDRA determines the primary direction for each port A pin. A 1 causes the associated port pin to be an
output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects
the source of data for reads of the corresponding PORTA register. If the DDR bit is 0 (input) the buffered
pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally. It is reset to 0x00 so the DDR does not override the three-state control
signals.
136
Module Base + 0x0002
Starting address location affected by INITRG register setting.
Reset
DDRA
Field
7:0
W
R
Bit 7
Data Direction Port A
0 Configure the corresponding I/O pin as an input
1 Configure the corresponding I/O pin as an output
Data Direction Register A (DDRA)
0
7
6
0
6
Figure 4-4. Data Direction Register A (DDRA)
Table 4-3. DDRA Field Descriptions
MC9S12C-Family / MC9S12GC-Family
5
0
5
Rev 01.24
4
0
4
Description
3
0
3
2
0
2
Freescale Semiconductor
1
0
1
Bit 0
0
0
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