MC9S12C96CFUE Freescale Semiconductor, MC9S12C96CFUE Datasheet - Page 180
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MC9S12C96CFUE
Manufacturer Part Number
MC9S12C96CFUE
Description
IC MCU 96K FLASH 4K RAM 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C96CFUE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
60
Number Of Timers
8
Operating Supply Voltage
- 0.3 V to + 6.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C96CFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC9S12C96CFUER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 6 Background Debug Module (BDMV4) Block Description
earlier. Synchronization between the host and target is established in this manner at the start of every bit
time.
Figure 6-7
target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten
target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic
requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1
transmission.
Because the host drives the high speedup pulses in these two cases, the rising edges look like digitally
driven signals.
The receive cases are more complicated.
system. Because the host is asynchronous to the target, there is up to one clock-cycle delay from the host-
generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
180
START OF BIT TIME
TARGET SYSTEM
TRANSMIT 1
TRANSMIT 0
PERCEIVED
CLOCK
HOST
HOST
shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a
SYNCHRONIZATION
UNCERTAINTY
Figure 6-7. BDM Host-to-Target Serial Bit Timing
MC9S12C-Family / MC9S12GC-Family
Figure 6-8
10 CYCLES
Rev 01.24
TARGET SENSES BIT
shows the host receiving a logic 1 from the target
Freescale Semiconductor
EARLIEST
START OF
NEXT BIT
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