MC9S12XEQ384CAL Freescale Semiconductor, MC9S12XEQ384CAL Datasheet - Page 488
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MC9S12XEQ384CAL
Manufacturer Part Number
MC9S12XEQ384CAL
Description
MCU 16BIT 384K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEQ384CAL
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
24 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
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MC9S12XEQ384CAL
Manufacturer:
FREESCAL
Quantity:
256
Company:
Part Number:
MC9S12XEQ384CAL
Manufacturer:
Freescale Semiconductor
Quantity:
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Manufacturer:
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20 000
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
11.4
11.4.1
11.4.1.1
The IPLL is used to run the MCU from a different time base than the incoming OSCCLK.
shows a block diagram of the IPLL.
For increased flexibility, OSCCLK can be divided in a range of 1 to 64 to generate the reference frequency
REFCLK using the REFDIV[5:0] bits. This offers a finer multiplication granularity. Based on the
SYNDIV[5:0] bits the IPLL generates the VCOCLK by multiplying the reference clock by a multiple of
2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,4,6,8,...
to 62 to generate the PLLCLK.
Several examples of IPLL divider settings are shown in
settings are not recommended. The following rules help to achieve optimum stability and shortest lock
time:
488
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
.
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
•
•
EXTAL
XTAL
Use lowest possible f
Use highest possible REFCLK frequency f
Supplied by:
Functional Description
Functional Blocks
Phase Locked Loop with Internal Filter (IPLL)
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
V
V
CONSUMPTION
DDPLL
DD
OSCILLATOR
REDUCED
/V
If (PLLSEL = 1) then f
IF POSTDIV = $00 the f
SS
/V
SSPLL
OSCCLK
VCO
MONITOR
f PLL
CLOCK
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 11-15. IPLL Functional Diagram
/ f
=
REF
2 f OSC
PROGRAMMABLE
×
REFERENCE
ratio (SYNDIV value).
REFDIV[5:0]
DIVIDER
BUS
PLL
PROGRAMMABLE
= f
SYNDIV[5:0]
×
DIVIDER
is identical to f
LOOP
----------------------------------------------------------------------------- -
[
PLL
REFDIV
NOTE
REF
/ 2.
REFCLK
.
Table
SYNDIV
FBCLK
+
1
] 2 POSTDIV
[
11-14. Shaded rows indicated that these
VCO
×
DETECTOR
DETECTOR
+
PHASE
1
LOCK
PDET
(divide by one)
PROGRAMMABLE
POSTDIV[4:0]
DIVIDER
POST
]
DOWN
UP
VCOCLK
LOCK
CPUMP
FILTER
AND
Freescale Semiconductor
V
DDPLL
Figure 11-15
/V
PLLCLK
SSPLL
VCO
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