MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 121

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.4
The V1 ColdFire core can perform higher speed I/O via its local bus, which does not have latency penalties
associated with the on-chip peripheral bus bridge. The Rapid GPIO module contains separate set/clear/data
registers based at address 0x(00)C0_0000. This functionality can be programmed to take priority on ports
A and B.
This functionality is further defined in
4.5
The block diagram for each keyboard interrupt logic is shown
Writing to KBIxPE[KBIPEn] independently enables or disables each port pin. Each port can be configured
as edge-sensitive or edge- and level-sensitive based on the KBIxSC[KBIMOD] bit. Edge sensitivity can
be software programmed to be falling or rising; the level can be either low or high. The polarity of the
edge-sensitivity or edge- and level-sensitivity is selected using the KBIxES[KBEDGn].
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled port inputs must be at the
deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic 1 (the
deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising
edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during
the next cycle.
Freescale Semiconductor
KBIxP0
KBIxPn
PTxTOGn
KBEDG0
KBEDGn
Field
7–0
V1 ColdFire Rapid GPIO Functionality
Keyboard Interrupts
1
0
1
0
S
S
TOG Port x Bits — These write only bits toggle a GPIO output.
0 Do not change the state of the GPIO pin
1 Toggle PTxD
KBIPE0
KBIPEn
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 4-12. Port Interrupt Block Diagram
Table 4-16. PTxTOG Field Descriptions
Chapter 5, “Rapid GPIO (RGPIO).”
KBIMOD
VDD
D
CK
CLR
Description
Q
INTERRUPT FF
KEYBOARD
Figure
KBACK
RESET
4-12.
STOP
SYNCHRONIZER
STOP BYPASS
BUSCLK
KBIE
KBF
KBI
INTERRUPT
REQUEST
4-11