MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 194

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ColdFire Core
instruction, fetches the required operands, and then executes the required function. Because the IFP and
OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch
instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for
instructions.
The V1 ColdFire core pipeline stages include the following:
When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the operand
execution pipeline. If the buffer is not empty, the IFP stores the contents of the fetched instruction in the
IB until it is required by the OEP. The instruction buffer on the V1 core contains three longwords of
storage.
For register-to-register and register-to-memory store operations, the instruction passes through both OEP
stages once. For memory-to-register and read-modify-write memory operations, an instruction is
effectively staged through the OEP twice; the first time to calculate the effective address and initiate the
operand fetch on the processor’s local bus, and the second time to complete the operand reference and
perform the required function defined by the instruction.
The resulting pipeline and local bus structure allow the V1 ColdFire core to deliver sustained high
performance across a variety of demanding embedded applications.
8.2
The following sections describe the processor registers in the user and supervisor programming models.
The programming model is selected based on the processor privilege level (user mode or supervisor mode)
as defined by the S bit of the status register (SR).
The user-programming model consists of the following registers:
8-2
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•
•
•
•
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Two-stage instruction fetch pipeline (IFP) (plus optional instruction buffer stage)
— Instruction address generation (IAG) — Calculates the next prefetch address
— Instruction fetch cycle (IC)—Initiates prefetch on the processor’s local bus
— Instruction buffer (IB) — Optional buffer stage minimizes fetch latency effects using FIFO
Two-stage operand execution pipeline (OEP)
— Decode and select/operand fetch cycle (DSOC)—Decodes instructions and fetches the
— Address generation/execute cycle (AGEX)—Calculates operand address or executes the
16 general-purpose 32-bit registers (D0–D7, A0–A7)
32-bit program counter (PC)
8-bit condition code register (CCR)
MAC registers
— One 32-bit accumulator(ACC) register
— One 16-bit mask register (MASK)
— 8-bit Status register (MACSR)
Memory Map/Register Description
queue
required components for effective address calculation, or the operand fetch cycle
instruction
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
(described fully in
Chapter 9, “Multiply-Accumulate Unit
Table 8-1
lists the processor registers.
(MAC)”)
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